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RL78/D1A User's Manual: Hardware - Renesas

RL78/D1A User's Manual: Hardware - Renesas

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Under development<br />

Preliminary document<br />

Specifications in this document are tentative and subject to change.<br />

<strong>RL78</strong>/<strong>D1A</strong> CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF)<br />

Figure 13-17. Format of LIN-UARTn Buffer Control Register (UFnBUCTL) (2/2)<br />

UFnNO No-response request bit<br />

0 Response for received PID is present.<br />

1 Response for received PID is absent.<br />

The UFnNO bit is used when a PID (PID received by a header) stored into the UFnID register is<br />

excluded in automatic baud rate mode (UFnMD1, UFnMD0 = 11B). After setting the UFnNO bit, the<br />

bit will be cleared automatically when the next BF-SF reception is complete. It can be set only in<br />

automatic baud rate mode (UFnMD1, UFnMD0 = 11B). The UFnNO bit is automatically cleared at<br />

the reception complete timing after the next BF and SF are received.<br />

See 13.7 LIN Communication Automatic Baud Rate Mode for details.<br />

Caution Do not set the UFnTRQ and UFnRRQ bits while the UFnNO bit is “1”.<br />

Simultaneous rewriting is prohibited.<br />

UFnRRQ Reception request bit<br />

0 Storing has been started/no reception request<br />

1 Reception start request/during receive operation in automatic baud rate mode<br />

The UFnRRQ bit is used to request starting of storing data into a buffer. It is cleared when a<br />

reception completion interrupt for the buffer is generated. It can be set only in automatic baud rate<br />

mode (UFnMD1, UFnMD0 = 11B).<br />

See 13.7 LIN Communication Automatic Baud Rate Mode for details.<br />

Caution Do not set the UFnNO and UFnTRQ bits while the UFnRRQ bit is “1”.<br />

Simultaneous rewriting is prohibited.<br />

UFnTRQ Transmission request bit<br />

0 Storing has been started/no transmission request<br />

1 Transmission start request/during transmit operation when using buffer<br />

The UFnTRQ bit is used to request starting of transmitting buffer data. It is cleared when a<br />

transmission interrupt for the data prepared in the buffer is generated. It can be set only in normal<br />

UART mode (UFnMD1, UFnMD0 = 00B) or automatic baud rate mode (UFnMD1, UFnMD0 = 11B).<br />

See 13.6.1 UART buffer mode transmission and 13.7 LIN Communication Automatic Baud<br />

Rate Mode for details.<br />

Caution Do not set the UFnNO and UFnRRQ bits while the UFnTRQ bit is “1”.<br />

Simultaneous rewriting is prohibited.<br />

UFnBUL3 to UFnBUL0 Buffer length bits<br />

0 Transmits or receives 9 bytes.<br />

1 to 9 Transmits or receives number of bytes set.<br />

10 to 15 Transmits or receives 9 bytes.<br />

The UFnBUL3 to UFnBUL0 bits are used to set the number of transmit or receive data in a buffer.<br />

The read value is the pointer of the current buffer. The bits are valid only in normal UART mode<br />

(UFnMD1, UFnMD0 = 00B) or automatic baud rate mode (UFnMD1, UFnMD0 = 11B).<br />

See 13.6.1 UART buffer mode transmission and 13.7 LIN Communication Automatic Baud<br />

Rate Mode for details.<br />

R01UH0317EJ0004 Rev. 0.04 712<br />

Feb. 22, 2013

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