RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 14 CAN CONTROLLER (12) CAN module interrupt status register (C0INTS, C1INTS) The C0INTS, C1INTS register indicates the interrupt status of the CAN module. (a) Read (b) Write (a) Read (b) Write Figure 14-36. Format of CAN Module Interrupt Status Register (C0INTS, C1INTS) Address: F05E8H (C0INTS), F0398H (C1INTS) After reset: 0000H R/W C0INTS, C1INTS C0INTS, C1INTS 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 CINTS5 CINTS4 CINTS3 CINTS2 CINTS1 CINTS0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 Clear CINTS5 Clear CINTS4 Clear CINTS3 Clear CINTS2 CINTS5-CINTS0 CAN Interrupt Status Bit 0 No related interrupt source event is pending. 1 A related interrupt source event is pending. Interrupt Status Bit Related Interrupt Source Event CINTS5 Wakeup interrupt from CAN sleep mode Note CINTS4 Arbitration loss interrupt CINTS3 CAN protocol error interrupt CINTS2 CAN error status interrupt Clear CINTS1 Clear CINTS0 CINTS1 Interrupt on completion of reception of valid message frame to message buffer m CINTS0 Interrupt on normal completion of transmission of message frame from message buffer m Note The CINTS5 bit is set only when the CAN module is woken up from the CAN sleep mode by a CAN bus operation. The CINTS5 bit is not set when the CAN sleep mode has been released by software. Clear CINTS5-CINTS0 0 CINTS5 to CINTS0 bits are not changed. 1 CINTS5 to CINTS0 bits are cleared to 0. Setting of CINTS5 to CINTS0 Bits Caution Please clear the status bit of this register with software when the confirmation of each status is necessary in the interrupt processing, because these bits are not cleared automatically. R01UH0317EJ0004 Rev. 0.04 861 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 14 CAN CONTROLLER (13) CAN module bit rate prescaler register (C0BRP, C1BRP) The C0BRP, C1BRP register is used to select the CAN protocol layer basic clock (fTQ). The communication baud rate is set to the C0BTR, C1BTR register. Figure 14-37. Format of CAN Module Bit Rate Prescaler Register (C0BRP, C1BRP) Address: F05EAH (C0BRP), F039AH (C1BRP) After reset: FFH R/W C0BRP, C1BRP 7 6 5 4 3 2 1 0 TQPRS7 TQPRS6 TQPRS5 TQPRS4 TQPRS3 TQPRS2 TQPRS1 TQPRS0 TQPRS7-TQPRS0 CAN Protocol Layer Basic System Clock (fTQ) 0 fCANMOD/1 1 fCANMOD/2 : : n fCANMOD/(n+1) : : 255 fCANMOD/256 (default value) Prescaler 0 Figure 14-38. CAN Global Clock CAN global module clock select register (C0GMCS, C0GMCS) Baud rate generator CCP3 CCP2 CCP1 CCP0 fCAN fCANMOD fTQ 0 0 0 CAN bit-rate register (C0BTR, C1BTR) TQPRS7 TQPRS6 TQPRS5 TQPRS4 TQPRS3 TQPRS2 TQPRS1 CAN module bit-rate prescaler register (C0BRP, C1BRP) Caution The CPBRP register can be write-accessed only in the initialization mode. Remark fCAN: Clock supplied to CAN (fMAIN) fCANMOD: CAN module system clock fTQ: CAN protocol layer basic system clock TQPRS0 R01UH0317EJ0004 Rev. 0.04 862 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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