RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF)
When the LRxDn pin is sampled by using the operating clock and a falling edge is detected, data sampling of the
LRxDn pin is started and is recognized as a start bit if it is at low level at a timing of half the reception baud rate clock
period after the falling edge has been detected. When the start bit has been recognized, a reception operation is started
and serial data is sequentially stored into the receive shift register according to the baud rate set. When a stop bit has
been received, the data stored into the receive shift register is transferred to the receive data register (UFnRX) at the
same time a reception complete interrupt request signal (INTLRn) is generated.
When an overrun error has occurred (UFnOVE = 1), however, the receive data is not transferred to the UFnRX register
but discarded. When any other error has occurred, the reception is continued up to the reception position of the stop bit
and the receive data is transferred to the UFnRX register.
After the occurrence of any reception error, INTLSn is generated after completion of the reception and INTLRn is not
generated.
fCLK
Figure 13-27. Data Reception Timing Chart
LRxDn pin START DT0 DTn STOP1
Sampling point
Prescaler clock
Reception baud rate clock
INTLRn (error-free)
INTLSn (error)
Note
Reception baud rate
clock period
UFnRX register New data
UFnRSF flag
Note One-half the reception baud rate clock period
Reception processing start
Reception processing
end
Reception baud rate
clock period
Cleared upon detection of first stop bit
Cautions 1. The start bit is not recognized when a high level is detected at a timing of half the reception baud
rate clock period after the falling edge of the LRxDn pin was detected.
2. A reception always operates with the number of stop bits as 1.
At that time, the second stop bit is ignored.
3. When a low level is constantly input to the LRxDn pin before an operation to enable reception is
performed, the receive data is not identified as a start bit.
4. For successive reception, the next start bit can be detected immediately after a stop bit of the first
receive data has been detected (upon generation of a reception complete interrupt).
5. Be sure to enable reception (UFnRXE = 1) after having changed the UFnRDL bit. If the UFnRDL
bit is changed after having enabled reception, the start bit may be detected falsely.
Remark n = 0, 1
R01UH0317EJ0004 Rev. 0.04 724
Feb. 22, 2013