RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A APPENDIX A NUMBER OF WAIT CYCLES TO ACCESS I/O REGISTERS APPENDIX A NUMBER OF WAIT CYCLES TO ACCESS I/O REGISTERS R01UH0317EJ0004 Rev. 0.04 1279 Feb. 22, 2013
R01UH0317EJ0004 Rev. 0.04 1280 Feb. 22, 2013 Necessary WAIT I/O register(SFR) name R/W Bit R/W Address READ(MIN.) READ(MAX.) WRITE(MIN.) WRITE(MAX.) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1 8 16 7 6 5 4 3 2 1 0 - - - - F0010 ADM2 (A/D converter mode register 2) E E - E E E R E E R E ADREFP1 ADREFP0 ADREFM ADRCK AWC ADTYP E E E E E - E - - - - F0011 ADUL (Conversion result comparison upper limit setting register ) - E - - - - - - - - - - - - - F0012 ADLL (Conversion result comparison lower limit setting register) - E - - - - - - - - - - - - - F0013 ADTES (AD test register) - E - - - - - - - - - - - - - F0030 - - - - F0031 - - - - F0033 - - - - F0034 - - - - F0035 - - - - F0036 - - - - F0037 - - - - F0038 - - - - F0039 - - - - F003D - - - - F003E - - - - F0040 - - - - F0041 PU0 (Pull-up resistor option register 0) E E - E E E E E E E E PU0_7 PU0_6 PU0_5 PU0_4 PU0_3 PU0_2 PU0_1 PU0_0 E E E E E E E E PU1 (Pull-up resistor option register 1) E E - E E E E E E E E PU1_7 PU1_6 PU1_5 PU1_4 PU1_3 PU1_2 PU1_1 PU1_0 E E E E E E E E PU3 (Pull-up resistor option register 3) E E - E E E E E E E E PU3_7 PU3_6 PU3_5 PU3_4 PU3_3 PU3_2 PU3_1 PU3_0 E E E E E E E E PU4 (Pull-up resistor option register 4) E E - R R R R R R R E PU4_0 - - - - - - - E PU5 (Pull-up resistor option register 5) E E - E E E E E E E E PU5_7 PU5_6 PU5_5 PU5_4 PU5_3 PU5_2 PU5_1 PU5_0 E E E E E E E E PU6 (Pull-up resistor option register 6) E E - R E E E E E E E PU6_6 PU6_5 PU6_4 PU6_3 PU6_2 PU6_1 PU6_0 - E E E E E E E PU7 (Pull-up resistor option register 7) E E - R R E E E E E E PU7_5 PU7_4 PU7_3 PU7_2 PU7_1 PU7_0 - - E E E E E E PU8 (Pull-up resistor option register 8) E E - E E E E E E E E PU8_7 PU8_6 PU8_5 PU8_4 PU8_3 PU8_2 PU8_1 PU8_0 E E E E E E E E PU9 (Pull-up resistor option register 9) E E - E E E E E E E E PU9_7 PU9_6 PU9_5 PU9_4 PU9_3 PU9_2 PU9_1 PU9_0 E E E E E E E E PU13 (Pull-up resistor option register 13) E E - R E E E E E E R PU13_6 PU13_5 PU13_4 PU13_3 PU13_2 PU13_1 - E E E E E E - PU14 (Pull-up resistor option register 14) E E - R R R R R R R E PU14_0 - - - - - - - E PIM0 (Port intput mode register 0 ) E E - R R R R R R E R PIM0_1 - - - - - - E - PIM1 (Port intput mode register 1) E E - E R R R R R E E PIM1_7 PIM1_1 PIM1_0 E - - - - - E 1280 RL78/D1A APPENDIX A NUMBER OF WAIT CYCLES TO ACCESS I/O REGISTERS Specifications in this document are tentative and subject to change. Under development Preliminary document
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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12.5.3 Master transmission/receptio
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19.2 Configuration of DMA Controlle
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RL78/D1A User’s Manual: Hardware
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RL78/D1A User's Manual: Hardware - Renesas

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