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RL78/D1A User's Manual: Hardware - Renesas

RL78/D1A User's Manual: Hardware - Renesas

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Under development<br />

Preliminary document<br />

Specifications in this document are tentative and subject to change.<br />

<strong>RL78</strong>/<strong>D1A</strong> CHAPTER 6 TIMER ARRAY UNIT<br />

fCLK<br />

Peripheral enable<br />

register 0<br />

(PER0)<br />

4 4<br />

TAU0EN<br />

Timer clock select register 0 (TPS0)<br />

Channel 0<br />

Selector<br />

Figure 6-1. Block Diagram of Timer Array Unit 0<br />

PRS033 PRS032 PRS031 PRS030 PRS023 PRS022 PRS021 PRS020PRS013<br />

PRS012 PRS011 PRS010 PRS003 PRS002 PRS001 PRS000<br />

TI00<br />

TI01<br />

(timer<br />

input<br />

pin Note )<br />

TI02<br />

TI03<br />

TI04<br />

TI05<br />

TI06<br />

TI07<br />

Noise elimination<br />

enabled/disabled<br />

CK00<br />

Channel 2<br />

Channel 3<br />

Channel 4<br />

Channel 5<br />

Channel 6<br />

4 4<br />

fCLK/2 0 to fCLK/2 15<br />

Selector<br />

CK01 fMCK fTCLK<br />

CK02<br />

CK03<br />

TNFEN01<br />

Operation clock<br />

selection<br />

Channel 1<br />

Channel 7<br />

fCLK/2 0 to fCLK/2 15<br />

Edge<br />

detection<br />

Selector<br />

Prescaler<br />

Slave/master<br />

controller<br />

Slave/master<br />

controller<br />

Trigger signal to slave channel<br />

Clock signal to slave channel<br />

Interrupt signal to slave channel<br />

Count clock<br />

selection<br />

Trigger<br />

selection<br />

Selector<br />

Timer controller<br />

Mode<br />

selection<br />

TE07 TE06 TE05 TE04 TE03 TE02 TE01 TE00<br />

TS07 TS06 TS05 TS04 TS03 TS02 TS01 TS00<br />

TT07 TT06 TT05 TT04 TT03 TT02 TT01 TT00<br />

Timer output enable<br />

TOE07 TOE06 TOE05 TOE04 TOE03 TOE02 TOE01 TOE00 register 0 (TOE0)<br />

TO07 TO06 TO05 TO04 TO03 TO02 TO01 TO00<br />

Timer channel enable<br />

status register 0 (TE0)<br />

Timer channel start<br />

register 0 (TS0)<br />

Timer channel stop<br />

register 0 (TT0)<br />

Timer output<br />

register 0 (TO0)<br />

Timer output mode<br />

TOM07 TOM06TOM05 TOM04 TOM03 TOM02TOM01 TOM00<br />

register 0 (TOM0)<br />

Timer output level<br />

TOL07 TOL06 TOL05 TOL04 TOL03 TOL02 TOL01 TOL00<br />

register 0 (TOL0)<br />

Output controller<br />

Interrupt<br />

controller<br />

Timer counter register 01 (TCR01)<br />

Timer data register 01 (TDR01)<br />

CKS010 CCS01 MAS<br />

TER01 STS012<br />

CKS011<br />

STS011 STS010 CIS011CIS010 MD013 MD012 MD011 MD010<br />

Timer mode register 01 (TMR01)<br />

Timer status<br />

register 01 (TSR01)<br />

OVF<br />

Overflow 01<br />

Note See Figure 6-2 for timer input pin selection and timer output pin selection.<br />

R01UH0317EJ0004 Rev. 0.04<br />

Feb. 22, 2013<br />

319<br />

TO00<br />

INTTM00<br />

TO01<br />

(timer output pin Note )<br />

INTTM01<br />

(timer interrupt)<br />

TO02<br />

INTTM02<br />

TO03<br />

INTTM03<br />

TO04<br />

INTTM04<br />

TO05<br />

INTTM05<br />

TO06<br />

INTTM06<br />

TO07<br />

INTTM07

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