RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 5 CLOCK GENERATOR 5.7.5 CPU clock status transition diagram Figure 5-20 shows the CPU clock status transition diagram of this product. Figure 5-20. CPU Clock Status Transition us Transition Diagram fIH: Run fMX: Selectable fSUB: Selectable fIL: Selectable by option byte PLL: Run fIH: Run fMX: Selectable fSUB: Selectable fIL: Selectable by option byte PLL: Run fIH: Stop fMX: Stop fSUB: Selectable fIL: Selectable by option byte PLL: Stop fIH: Selectable fMX: Selectable fSUB: Run fIL: Selectable by option byte PLL: Stop fIH: Selectable fMX: Selectable fSUB: Run fIL: Selectable by option byte PLL: Stop fPLL HALT fPLL STOP fPLL RUN fXT HALT fXT RUN fIH: Selectable fMX: Run fSUB: Selectable fIL: Selectable by option byte PLL: Run fIH: Run fMX: Selectable fSUB: Selectable fIL: Selectable by option byte PLL: Stop fIH: Selectable fMX: Run fSUB: Selectable fIL: Selectable by option byte PLL: Run fPLL HALT Power ON Reset sequence fIH RUN fMX RUN fPLL RUN fIH: Selectable fMX: Run fSUB: Selectable fIL: Selectable by option byte PLL: Stop fPLL STOP fMX HALT fMX STOP fIH: Stop Note fMX: Stop fSUB: Selectable fIL: Selectable by option byte PLL: Stop The route of "fIH RUN fXT RUN fMX RUN" and "fMX RUN fXT RUN fIH RUN" is not allowed. Table 5-5 shows transition of the CPU clock and examples of setting the SFR registers. fIH HALT fIH STOP Table 5-5. CPU Clock Transition and SFR Register Setting Examples (1/6) (1) CPU operating with high-speed on-chip oscillator clock (B) after reset release (A) Status Transition SFR Register Setting fH: Run fMX: Selectable fSUB: Selectable fIL: Selectable by option byte PLL: Stop fIH: Stop fMX: Stop fSUB: Selectable fIL: Selectable by option byte PLL: Stop fIH: Selectable fMX: Run fSUB: Selectable fIL: Selectable by option byte PLL: Stop fIH: Stop fMX: Stop fSUB: Selectable fIL: Selectable by option byte PLL: Stop (A) (B) SFR registers do not have to be set (default status after reset release). R01UH0317EJ0004 Rev. 0.04 303 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 5 CLOCK GENERATOR Table 5-5. CPU Clock Transition and SFR Register Setting Examples (2/6) (2) CPU operating with high-speed system clock (C) after reset release (A) (The CPU operates with the high-speed on-chip oscillator clock immediately after a reset release (B).) (Setting sequence of SFR registers) CMC Register Note1 Setting Flag of SFR Register OSTS CSC Register Register Status Transition EXCLK OSCSEL AMPH MSTOP (A) (B) (C) (X1 clock: 1 MHz fX 10 MHz) (A) (B) (C) (X1 clock: 10 MHz < fX 20 MHz) (A) (B) (C) (external main clock) 0 1 0 0 1 1 1 1 OSTC Register R01UH0317EJ0004 Rev. 0.04 304 Feb. 22, 2013 Note 2 CKC Register MCM0 0 Must be checked 1 Note 2 0 Must be checked 1 Note 2 0 Must not be checked 1 Note 1. The clock operation mode control register (CMC) can be written only once by an 8-bit memory manipulation instruction after reset release. 2. Set the oscillation stabilization time as follows. Desired the oscillation stabilization time counter status register (OSTC) oscillation stabilization time Oscillation stabilization time set by the oscillation stabilization time select register (OSTS) Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see CHAPTER 32 ELECTRICAL SPECIFICATIONS (J GRADE PRODUCT) (TARGET) and CHAPTER 33 ELECTRICAL SPECIFICATIONS (L GRADE PRODUCT) (TARGET). (3) CPU operating with subsystem clock (D) after reset release (A) (The CPU operates with the high-speed on-chip oscillator clock immediately after a reset release (B).) Status Transition (A) (B) (D) (XT1 clock) (A) (B) (D) (external sub clock) (Setting sequence of SFR registers) Setting Flag of SFR Register CMC Register Note CSC Register OSCSELS AMPHS1 AMPHS0 XTSTOP Waiting for Oscillation Stabilization CKC Register 1 0/1 0/1 0 Necessary 1 1 0 Necessary 1 Note The clock operation mode control register (CMC) can be written only once by an 8-bit memory manipulation instruction after reset release. Remarks 1. ×: don’t care 2. (A) to (J) in Table 5-5 correspond to (A) to (J) in Figure 5-20. CSS
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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34.2 64-pin products 1276 R5F10CLDx
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RL78/D1A User’s Manual: Hardware
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