RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 14 CAN CONTROLLER 14.7 Control Registers Remark m = 0 to 15 (1) Peripheral clock select register (PCKSEL) This register is used to select for and supply to each peripheral hardware device the operating clock. PCKSEL can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Caution Set the PCKSEL register before starting to operate each peripheral hardware device. Figure 14-25. Format of Peripheral Clock Select Register (PCKSEL) Address: F00F2H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 PCKSEL 0 CAN MCKE1 CAN MCK1 CAN MCKE0 R01UH0317EJ0004 Rev. 0.04 843 Feb. 22, 2013 CAN MCK0 CANMCKEn CANMCKn aFCANn input clock control n = 0, 1 0 X STOPS input clock supply. 1 0 fMAIN is supplied 1 1 fMP is supplied Writing to SFR to be used with aFCANn is disabled 0 0 SGCLK Reading from and writing to SFR to be used with aFCANn is enable Reading from and writing to SFR to be used with aFCANn is enable SEL
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 14 CAN CONTROLLER (2) CAN global module control register (C0GMCTRL, C1GMCTRL) The C0GMCTRL, C1GMCTRL register is used to control the operation of the CAN module. (a) Read (b) Write (a) Read Figure 14-26. Format of CAN Global Module Control Register (C0GMCTRL, C1GMCTRL) (1/2) Address: F05C0H (C0GMCTRL), F0340H (C1GMCTRL) After reset: 0000H R/W C0GMCTRL, C1GMCTRL C0GMCTRL, C1GMCTRL 15 14 13 12 11 10 9 8 MBON 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 EFSD GOM 15 14 13 12 11 10 9 8 0 0 0 0 0 0 Set EFSD R01UH0317EJ0004 Rev. 0.04 844 Feb. 22, 2013 Set GOM 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 Clear GOM MBON Bit Enabling Access to Message Buffer Register, Transmit/Receive History List Registers 0 Write access and read access to the message buffer register and the transmit/receive history list registers is disabled. 1 Write access and read access to the message buffer register and the transmit/receive history list registers is enabled. Cautions 1. While the MBON bit is cleared (to 0), software access to the message buffers (C0MDB0m, C1MDB0m, C0MDB1m, C1MDB1m, C0MDB01m, C1MDB01m, C0MDB2m, C1MDB2m, C0MDB3m, C1MDB3m, C0MDB23m, C1MDB23m, C0MDB4m, C1MDB4m, C0MDB5m, C1MDB5m, C0MDB45m, C1MDB45m, C0MDB6m, C1MDB6m, C0MDB7m, C1MDB7m, C0MDB67m, C1MDB67m, C0MDLCm, C1MDLCm, C0MCONFm, C1MCONFm, C0MIDLm, C1MIDLm, C0MIDHm, C1MIDHm, and C0MCTRLm, C1MCTRLm), or registers related to transmit history or receive history (C0LOPT, C1LOPT, C0TGPT, C1TGPT, C0LIPT, C1LIPT, and C0RGPT, C1RGPT) is disabled. 2. This bit is read-only. Even if 1 is written to MBON while it is 0, the value of MBON does not change, and access to the message buffer registers, or registers related to transmit history or receive history remains disabled. Remark MBON bit is cleared (to 0) when the CAN module enters CAN sleep mode/CAN stop mode or GOM bit is cleared (to 0). MBON bit is set (to 1) when the CAN sleep mode/the CAN stop mode is released or GOM bit is set (to 1).
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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