RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 5 CLOCK GENERATOR
5.4 Clock monitor (CLM)
The clock monitor uses the low-speed on-chip oscillator to sample the main system clock (fMAIN) and PLL clock(fPLL). If
oscillation of the main system clock stops, a reset request signal (RESFCLM) is generated. If the PLL clock stops, an
interrupt request signal (INTCLM) is generated. Up to 4 clocks of fIL is necessary to detect stop of Main OSC/PLL. After
detection, reset/interrupt request will immediately occurs.
When CLM macro monitors PLL clock (fPLL) and PLL clock stops, clock through is selected (original clock to PLL
input), but the FF/flag of SELPLL/SELPLLS itself is not cleared, so it is necessary to reset chip before select PLL clock
again.
Table 5-4: Clock Monitor Operation Conditions
Condition Optionbyte Clock monitor operation
fCLK=fSUB - Stop
fIL Stop - Stop
STOP mode - Stop
During oscillation
fCLK=fMP/2 stabilization after MCM0
setting
- Stop
CLKMB=1 Stop
N
fIL Operation
Other than above
CLKMB=0 Operation
As described in above table, fIL must be operated to activate CLM.
fIL operation is controled by the combination of below factor.
- WDSTBYON option byte
- WDTON option byte
- WUTMMCK0 bit
- Chip status (RUN/HALT/STOP/SNOOZE)
Please refer to the description of “Clock tree” for detail.
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Feb. 22, 2013