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RL78/D1A User's Manual: Hardware - Renesas

RL78/D1A User's Manual: Hardware - Renesas

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Under development<br />

Preliminary document<br />

Specifications in this document are tentative and subject to change.<br />

<strong>RL78</strong>/<strong>D1A</strong> CHAPTER 24 VOLTAGE DETECTOR<br />

24.4.3 When used as interrupt and reset mode<br />

When starting operation<br />

Specify the operation mode (the interrupt and reset (LVIMDS1, LVIMDS0 = 1, 0)) and the detection voltage<br />

(VLVDH, VLVDL) by using the option byte 000C1H/020C1H.<br />

Start in the following initial setting state.<br />

Set bit 7 (LVISEN) of the voltage detection register (LVIM) to 0 (disable rewriting of voltage detection level<br />

register (LVIS))<br />

When the option byte LVIMDS1 is set to 1 and LVIMDS0 is clear to 0, the initial value of the LVIS register is<br />

set to 00H.<br />

Bit 7 (LVIMD) is 0 (interrupt mode).<br />

Bit 0 (LVILV) is 0 (high-voltage detection level: VLVDH).<br />

Figure 24-6 shows the timing of the internal reset signal and interrupt signal generated by the voltage detector.<br />

Perform the processing according to Figure 24-7 Processing Procedure After an Interrupt Is Generated in<br />

interrupt and reset mode and Figure 24-8 Initial Setting of Interrupt and Reset Mode in interrupt and reset mode.<br />

R01UH0317EJ0004 Rev. 0.04 1124<br />

Feb. 22, 2013

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