RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 17 SOUND GENERATOR PWM generator The PWM generator modulates the duty cycle according to the desired volume. It is controlled by the volume register SG0PWM. The value written to this register is automatically copied to the associated volume compare buffer. The PWM generator continually compares the value of the counter S0GFL with the contents of its volume compare buffer. The RS flipflop of the PWM generator is set by the pulses generated by the counter S0GFL. It is reset when the SG0FL counter value matches the contents of the volume buffer. Thus, the PWM output signal can have a duty cycle between 0 % (null volume) and 100 % (maximum volume). The PWM frequency is above 32 kHz and hence outside the audible range. Outputs The Sound Generator is connected to the pins SGO and SGOA. By default, pin SGO provides the tone signal SG0OF and pin SGOA the PWM signal SG0OA that holds the volume (“amplitude”) information. If bit SG0CTL.OS is set, pin SGO provides the composite signal SG0O that can directly control a speaker circuit. These signal is output to one of the pin below. 48-pin products 64-pin products 80-pin products 100-pin products SGO/SGOF P93/P73 P93/P73 P93/P73 P93/P73/P135 SGOA P92/P72 P92/P72 P92/P72 P92/P72/P134 R01UH0317EJ0004 Rev. 0.04 999 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 17 SOUND GENERATOR 17.1.2 Principle of operation The software-controlled registers SG0FL, SG0FH, and SG0PWM are equipped with hardware buffers. The Sound Generator operates on these buffers. This approach eliminates audible artifacts, because the buffers are only updated in synchronization with the generated tone waveform. Remark This section provides an overview. For details please refer to 17.3 Sound Generator Operation. (1) Generation of the tone frequency The tone frequency is determined by two counters and their associated compare register values. Two counters are necessary to keep the tone pulse and the PWM signal synchronized. The first counter (S0GFL) provides the input to the tone generator and also to the PWM generator. It is used to keep the PWM frequency outside the audio range (above 30 kHz) and within the signal bandwidth of the external sound system (usually below 64 kHz). Its match value defines also the 100 % volume level. The second counter (S0GFH) generates the tone frequency (250 Hz to 6 kHz). Remark If the target values of the counters S0GFL/S0GFH are changed to generate a different tone frequency, the volume register SG0PWM has to be adjusted to keep the same volume. (2) Generation of the volume information The volume information (the “amplitude” of the audible signal) is provided as a high-frequency PWM signal. In composite mode, the PWM signal is ANDed with the tone signal, as illustrated in the following figure. Tone signal PWM signal, duty cycle 66 % Composite signal Analog audio signal Figure 17-2. Generation of the Composite Output Signal 100% 66% 0% After low-pass filtering, the analog signal amplitude corresponds to the duty cycle of the PWM signal. Low-pass filtering (averaging) is an inherent characteristic of a loudspeaker system. The duty cycle can vary between 0 % and 100 %. Its generation is controlled by the counter register SG0FL and the volume register SG0PWM. When the volume register SG0PWM is cleared, the sound stops immediately. R01UH0317EJ0004 Rev. 0.04 1000 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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6.8 Operation of Plural Channels of
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34.2 64-pin products 1276 R5F10CLDx
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RL78/D1A User’s Manual: Hardware
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