RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-61. Example of Set Contents of Registers When Frequency Divider Is Used (2/2) (d) Timer output level register m (TOLm) Bit n 0: Cleared to 0 when TOMmn = 0 (toggle mode). 0 TOLm TOLmn (e) Timer output mode register m (TOMm) Bit n 0: Sets toggle mode. 0 TOMm TOMmn Remark m: Unit number (m = 0 to 2) n: Channel number (n = 0 to 7) R01UH0317EJ0004 Rev. 0.04 417 Feb. 22, 2013
Operation is resumed. Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 6 TIMER ARRAY UNIT TAU default setting Channel default setting Operation start During operation Operation stop TAU stop Figure 6-62. Operation Procedure When Frequency Divider Function Is Used Software Operation Hardware Status Power-off status (Clock supply is stopped and writing to each register is disabled.) Sets the TAU0EN bit, TAU1EN bit of the PER0 register to 1. Power-on status. Each channel stops operating. (Clock supply is started and writing to each register is enabled.) Sets the TPSm register. Determines clock frequencies of CKm0 to CKm3. Sets the TMRmn register (determines operation mode of channel). Sets interval (period) value to the TDRmn register. Clears the TOMmn bit of the TOMm register to 0 (toggle mode). Clears the TOLmn bit to 0. Sets the TOmn bit and determines default level of the TOmn output. Sets TOEmn to 1 and enables operation of TOmn. Clears the port register and port mode register to 0. Sets the TOEmn to 1 (only when operation is resumed). Sets the TSmn bit to 1. The TSmn bit automatically returns to 0 because it is a trigger bit. Set value of the TDRmn register can be changed. The TCRmn register can always be read. The TSRmn register is not used. Set values of TOm and TOEm registers can be changed. Set values of TMRmn register, TOMmn, and TOLmn bits cannot be changed. The TTmn bit is set to 1. The TTmn bit automatically returns to 0 because it is a trigger bit. Channel stops operating. (Clock is supplied and some power is consumed.) The TOmn pin goes into Hi-Z output state. The TOmn default setting level is output when the port mode register is in output mode and the port register is 0. TOmn does not change because channel stops operating. The TOmn pin outputs the TOmn set level. TEmn = 1, and count operation starts. Value of TDRmn is loaded to TCRmn at the count clock input. INTTMmn is generated and TOmn performs toggle operation if the MDmn0 bit of the TMRmn register is 1. Counter (TCRmn) counts down. When count value reaches 0000H, the value of TDRmn is loaded to TCRmn again, and the count operation is continued. By detecting TCRmn = 0000H, INTTMmn is generated and TOmn performs toggle operation. After that, the above operation is repeated. TEmn = 0, and count operation stops. TCRmn holds count value and stops. The TOmn output is not initialized but holds current status. TOEmn is cleared to 0 and value is set to the TOmn bit. The TOmn pin outputs the TOmn set level. To hold the TOmn pin output level Clears TOmn bit to 0 after the value to be held is set to the port register. When holding the TOmn pin output level is not necessary Switches the port mode register to input mode. The TAU0EN bit, TAU1EN bit of the PER0 register are cleared to 0. Remark m: Unit number (m = 0 to 2) n: Channel number (n = 0 to 7) The TOmn pin output level is held by port function. The TOmn pin output level goes into Hi-Z output state. Power-off status All circuits are initialized and SFR of each channel is also initialized. (The TOmn bit is cleared to 0 and the TOmn pin is set to port mode). R01UH0317EJ0004 Rev. 0.04 418 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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34.2 64-pin products 1276 R5F10CLDx
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RL78/D1A User’s Manual: Hardware
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