RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 6 TIMER ARRAY UNIT Master channel Slave channel fCLK Count clock INTTMmn to_reset (Internal signal) TOmn pin/ TOmn to_set (Internal signal) INTTMmp to_reset (Internal signal) TOmp pin/ TOmp Figure 6-45. Set/Reset Timing Operating Statuses Toggle Delays to_reset by 1 count clock with slave channel Set Reset Remarks 1. to_reset: TOmn pin reset/toggle signal to_set: TOmn pin set signal 2. m: Unit number (m = 0 to 2), n: Channel number, p: Slave channel number R01UH0317EJ0004 Rev. 0.04 397 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 6 TIMER ARRAY UNIT 6.4.4 Collective manipulation of TOmn bits In the TOm register, the setting bits (TOmn) for all the channels are located in one register in the same way as the TSm register (channel start trigger). Therefore, TOmn of all the channels can be manipulated collectively. Only specific bits can also be manipulated by setting the corresponding TOEmn = 0 to a target TOmn (channel output). Before writing Figure 6-46. Example of TO0n Bits Collective Manipulation TO0 0 0 0 0 0 0 0 0 TO07 TOE0 0 0 0 0 0 0 0 0 TOE07 TOE06 TOE05 TOE04 TOE03 TOE02 TOE01 TOE00 After writing Data to be written R01UH0317EJ0004 Rev. 0.04 398 Feb. 22, 2013 0 0 TO06 0 0 TO05 1 1 TO04 0 0 TO03 0 1 TO02 0 1 TO01 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 TO0 0 0 0 0 0 0 0 0 TO07 Writing is done only to TOmn bits with TOEmn = 0, and writing to TOmn bits with TOEmn = 1 is ignored. TOmn (channel output) to which TOEmn = 1 is set is not affected by the write operation. Even if the write operation is done to TOmn, it is ignored and the output change by timer operation is normally done. TO07 TO06 TO05 TO04 TO03 TO02 TO01 TO00 1 TO06 1 TO05 1 TO04 0 TO03 Figure 6-47. TOmn Pin Statuses by Collective Manipulation of TO0n Bits Before writing Writing to TO0n register Two or more TO0n output can be changed simultaneously 0 Output does not change when value does not change Writing to TO0n register is ignored when TOE0n = 1 Caution When TOEmn = 1, even if the output by timer interrupt of each channel (INTTMmn) contends with writing to TOmn, output is normally done to TOmn pin. Remark m Unit number (m = 0 to 2) n: Channel number (n = 0 to 7) TO02 0 1 1 TO01 1 TO00 0 1 TO00 0
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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19.2 Configuration of DMA Controlle
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RL78/D1A User’s Manual: Hardware
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