RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF)
Figure 13-7. Format of LIN-UARTn Status Register (UFnSTR) (5/6)
UFnBSF Successful BF reception flag
0 BF reception is not successfully performed.
1 BF reception is successfully performed.
When successive low levels (BF) of at least 11 bits have been received
The UFnBSF bit is a flag indicating that receiving a BF has been performed successfully. It
becomes “1” when successive low levels (BF) of at least 11 bits have been received when in BF
reception enable mode during communication (UFnMD1, UFnMD0 = 10B) (This occurs at the
same time as the status interrupt (INTLSn) is issued upon the detection of the rising edge of the
LRXDn pin.).
The start of a new frame slot must be checked by reading the UFnBSF bit via status interrupt
servicing, because the BF may also be received during data communication when in BF
reception enable mode during communication.
The UFnBSF bit will not be cleared until “1” is written to the UFnCLBSF bit of the UFnSTC
register, because the UFnBSF bit is a cumulative flag. It will not be set when not in BF reception
enable mode during communication (UFnMD1, UFnMD0 = 10B).
UFnDCE Data consistency error flag
0 No data consistency error has occurred.
1 A data consistency error has occurred.
When transmit data and receive data do not match in LIN communication
When the data consistency check select bit is set (UFnDCS = 1), the transmit data and receive
data are compared upon data transmission. The UFnDCE bit becomes “1” at the same time as
the status interrupt (INTLSn) is issued when a mismatch has been detected.
The UFnDCE bit will not be cleared until “1” is written to the UFnCLDCE bit of the UFnSTC
register, because the UFnDCE bit is a cumulative flag. When UFnDCS is “0”, the UFnDCE bit will
not be set.
Caution The next transfer will not be performed if a data consistency error is detected. See
13.5.8 Data consistency check for details.
UFnPE Parity error flag
0 No parity error has occurred.
1 A parity error has occurred.
When parity of data and parity bit do not match during reception
The operation of the UFnPE bit depends on the settings of the UFnPS1 and UFnPS0 bits.
The UFnPE bit will not be cleared until “1” is written to the UFnCLPE bit of the UFnSTC register
or “0” is written to the UFnRXE bit of the UFnCTL0 register, because the UFnPE bit is a
cumulative flag. When UFnPS1 and UFnPS0 are “0xB”, the UFnPE bit will not be set. (x: Don’t
care)
R01UH0317EJ0004 Rev. 0.04 699
Feb. 22, 2013