RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
9.2 Configuration of Clock Output/Buzzer Output Controller
The clock output/buzzer output controller includes the following hardware.
Table 9-1. Configuration of Clock Output/Buzzer Output Controller
Item Configuration
Control registers Clock output select register 0 (CKS0)
Port mode register 7 (PM7)/6 (PM6)
Port register 7 (P7)/6 (P6)
9.3 Registers Controlling Clock Output/Buzzer Output Controller
The following registers are used to control the clock output/buzzer output controller.
Clock output select register 0 (CKS0)
Port mode register 7 (PM7)/6 (PM6)
(1) Clock output select register 0 (CKS0)
This register sets output enable/disable for clock output or for the buzzer frequency output pin (PCL), and set the
output clock.
Select the clock to be output from the PCL pin by using the CKS0 register.
The CKS0 register is set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
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Feb. 22, 2013