RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 14 CAN CONTROLLER
(2) Status in CAN sleep mode
The CAN module is in one of the following states after it enters the CAN sleep mode.
- The internal operating clock is stopped and the power consumption is minimized.
- The function to detect the falling edge of the CAN reception pin (CRxD) remains in effect to wake up the CAN
module from the CAN bus.
- To wake up the CAN module from the CPU, data can be written to PSMODE [1:0] of the CAN module control
register (C0CTRL), but nothing can be written to other CAN module registers or bits.
- The CAN module registers can be read, except for C0LIPT, C0RGPT, C0LOPT, and C0TGPT.
- The CAN message buffer registers cannot be written or read.
- MBON bit of the CAN0 Global Control register (C0GMCTRL) is cleared.
- A request for transition to the initialization mode is not acknowledged and is ignored.
(3) Releasing CAN sleep mode
The CAN sleep mode is released by the following events.
- When the CPU writes 00B to the PSMODE [1:0] bits of the C0CTRL register
- A falling edge at the CAN reception pin (CRxD) (i.e. the CAN bus level shifts from recessive to dominant)
Cautions 1. Even if the falling edge belongs to the SOF of a receive message, this message will not be
received and stored. If the CPU has turned off the clock to the CAN while the CAN was in
sleep mode, even subsequently the CAN sleep mode will not be released and PSMODE
[1:0] will continue to be 01B unless the clock to the CAN is supplied again. In addition to
this, the receive message will not be received after that.
2. If the falling edge on the CAN reception pin (CRxD) is detected in the state that the CAN
clock is supplied, it is necessary to clear the PSMODE0 bit by software (for details, refer to
the processing in Figure 14-81).
After releasing the sleep mode, the CAN module returns to the operation mode from which the CAN sleep mode
was requested and the PSMODE [1:0] bits of the C0CTRL register are reset to 00B. If the CAN sleep mode is
released by a change in the CAN bus state, the CINTS5 bit of the C0INTS register is set to 1, regardless of the
CIE bit of the C0IE register. After the CAN module is released from the CAN sleep mode, it participates in the
CAN bus again by automatically detecting 11 consecutive recessive-level bits on the CAN bus. The user
application has to wait until MBON = 1, before accessing message buffers again.
When a request for transition to the initialization mode is made while the CAN module is in the CAN sleep mode,
that request is ignored; the CPU has to be released from sleep mode by software first before entering the
initialization mode.
Caution Be aware that the release of CAN sleep mode by CAN bus event, and thus the wake up
interrupt may happen at any time, even right after requesting sleep mode, if a CAN bus event
occurs.
Remark m = 0 to 15
R01UH0317EJ0004 Rev. 0.04 901
Feb. 22, 2013