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RL78/D1A User's Manual: Hardware - Renesas

RL78/D1A User's Manual: Hardware - Renesas

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Under development<br />

Preliminary document<br />

Specifications in this document are tentative and subject to change.<br />

<strong>RL78</strong>/<strong>D1A</strong> CHAPTER 12 SERIAL ARRAY UNIT<br />

(2) Processing flow<br />

SSmn<br />

SEmn<br />

SOEmn<br />

SDRmn<br />

SCLr output<br />

SDAr output<br />

SDAr input<br />

Shift<br />

register mn<br />

INTIICr<br />

TSFmn<br />

“L”<br />

“H”<br />

“H”<br />

Figure 12-77. Timing Chart of Data Transmission<br />

D7 D6<br />

Transmit data 1<br />

D5 D4 D3 D2 D1 D0<br />

D7 D6 D5 D4 D3 D2 D1 D0<br />

R01UH0317EJ0004 Rev. 0.04 659<br />

Feb. 22, 2013<br />

Shift operation<br />

Remark m: Unit number (m = 1), n: Channel number (n = 1), r: IIC number (r = 11)<br />

No<br />

Figure 12-78. Flowchart of Data Transmission<br />

Address field<br />

transmission completed<br />

Starting data transmission<br />

Writing data to SDRmn<br />

Transfer end interrupt<br />

generated?<br />

Yes<br />

Parity error (ACK error) flag<br />

PEFmn = 1 ?<br />

No<br />

Data transfer completed?<br />

Yes<br />

Data transmission<br />

completed<br />

Stop condition generation<br />

No<br />

Yes<br />

ACK reception error<br />

ACK

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