RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 21 STANDBY FUNCTION (2) HALT mode release The HALT mode can be released by the following two sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgment is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgment is disabled, the next address instruction is executed. High-speed system clock, internal high-speed oscillation clock, or subsystem clock Figure 21-3. HALT Mode Release by Interrupt Request Generation Standby release signal Note1 Status of CPU Operating mode HALT instruction Interrupt request HALT mode Oscillation Wait Note2 Operating mode Notes 1. For details of the standby release signal, see Figure 20-1. Basic Configuration of Interrupt Function. 2. Wait time for HALT mode release When vectored interrupt servicing is carried out Main system clock: 15 to 16 clock Subsystem clock (RTCLPC = 0): 10 to 11 clock Subsystem clock (RTCLPC = 1): 11 to 12 clock When vectored interrupt servicing is not carried out Main system clock: 9 to 10 clock Subsystem clock (RTCLPC = 0): 4 to 5 clock Subsystem clock (RTCLPC = 1): 5 to 6 clock Remark The broken lines indicate the case when the interrupt request which has released the standby mode is acknowledged. R01UH0317EJ0004 Rev. 0.04 1081 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 21 STANDBY FUNCTION (b) Release by reset signal generation When the reset signal is generated, HALT mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address. Reset signal Status of CPU High-speed system clock (X1 oscillation) Reset signal Status of CPU High-speed on-chip oscillator clock Reset signal Status of CPU Subsystem clock (XT1 oscillation) Figure 21-4. HALT Mode Release by Reset (1) When high-speed system clock is used as CPU clock Normal operation (high-speed system clock) HALT instruction HALT mode Reset period Reset processing Note Normal operation (High-speed on-chip oscillator clock) Oscillates Oscillates Starting X1 oscillation is specified by software. (2) When high-speed on-chip oscillator clock is used as CPU clock HALT instruction Normal operation (High-speed on-chip oscillator clock) HALT mode Reset period Oscillates Oscillates Wait for oscillation accuracy stabilization (3) When subsystem clock is used as CPU clock HALT instruction Normal operation (subsystem clock) HALT mode Reset period R01UH0317EJ0004 Rev. 0.04 1082 Feb. 22, 2013 Reset processing Note Normal operation (High-speed on-chip oscillator clock) Reset processing Note Normal operation mode (High-speed on-chip oscillator clock) Oscillation stopped Oscillates Oscillates Note Reset processing time: 388 to 673 μ s (When LVD is used) 156 to 360 μ s (When LVD off) Starting XT1 oscillation is specified by software.
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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