RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 21 STANDBY FUNCTION Figure 21-5. STOP Mode Release by Interrupt Request Generation (2/2) (2) When high-speed system clock (external clock input) is used as CPU clock Standby release signal Status of CPU High-speed system clock (external clock input) Standby release signal Status of CPU High-speed on-chip oscillator clock Note 1 Normal operation (high-speed system clock) Oscillates STOP instruction Interrupt request STOP mode Oscillation stopped Oscillates Normal operation (high-speed system clock) R01UH0317EJ0004 Rev. 0.04 1087 Feb. 22, 2013 Wait (3) When high-speed on-chip oscillator clock is used as CPU clock Note 1 Oscillates STOP instruction Normal operation (high-speed on-chip oscillator clock) Interrupt request STOP mode Wait Oscillation stopped Oscillates Wait for oscillation accuracy stabilization Notes 1. For details of the standby release signal, see Figure 16-1 2. STOP mode release time Supply of the clock is stopped: 19.08 μs to 32.99 μs Wait When vectored interrupt servicing is carried out: 7 clocks When vectored interrupt servicing is not carried out: 1 clocks Normal operation (high-speed on-chip oscillator clock) Remark The broken lines indicate the case when the interrupt request that has released the standby mode is acknowledged.
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 21 STANDBY FUNCTION (b) Release by reset signal generation When the reset signal is generated, STOP mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address. Reset signal Status of CPU High-speed system clock (X1 oscillation) Reset signal Status of CPU High-speed on-chip oscillator clock Figure 21-6. STOP Mode Release by Reset (1) When high-speed system clock is used as CPU clock STOP instruction Normal operation (high-speed system clock) STOP mode Reset period Reset processing Note Normal operation (High-speed on-chip oscillator clock) Oscillates Oscillation stopped Oscillates Starting X1 oscillation is specified by software. (2) When high-speed on-chip oscillator clock is used as CPU clock Normal operation Oscillates STOP instruction STOP mode Oscillation stopped Note Reset processing time: 388 to 673 μs (When LVD is used) 156 to 360 μs (When LVD off) Reset period Wait for oscillation accuracy stabilization R01UH0317EJ0004 Rev. 0.04 1088 Feb. 22, 2013 Reset processing Note Normal operation (High-speed on-chip oscillator clock) Oscillates
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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19.2 Configuration of DMA Controlle
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