RL78/D1A User's Manual: Hardware - Renesas

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R01UH0317EJ0004 Rev. 0.04 1289 Feb. 22, 2013 Necessary WAIT I/O register(SFR) name R/W Bit R/W Address READ(MIN.) READ(MAX.) WRITE(MIN.) WRITE(MAX.) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1 8 16 7 6 5 4 3 2 1 0 - - - - F01A6 - - - - F01A8 - - - - F01AA - - - - F01AC - - - - F01AE - - - - F01B0 - - - - F01B2 - - - - F01B4 TSR03 (Timer status register 03) - - R - - - - - - - - TSR03L - R - - - - - - - - - TSR04 (Timer status register 04) - - R - - - - - - - - TSR04L - R - - - - - - - - - TSR05 (Timer status register 05) - - R - - - - - - - - TSR05L - R - - - - - - - - - TSR06 (Timer status register 06) - - R - - - - - - - - TSR06L - R - - - - - - - - - TSR07 (Timer status register 07) - - R - - - - - - - - TSR07L - R - - - - - - - - - TE0 (Timer channel enable status register0) - - R - - - - - - - - TE0L R R - R R R R R R R R TE0_7 TE0_6 TE0_5 TE0_4 TE0_3 TE0_2 TE0_1 TE0_0 R R R R R R R R TS0 (Timer channel start trigger register 0) - - E - - - - - - - - TS0L E E - E E E E E E E E TS0_7 TS0_6 TS0_5 TS0_4 TS0_3 TS0_2 TS0_1 TS0_0 E E E E E E E E TT0 (Timer channel stop trigger register 0) - - E - - - - - - - - TT0L E E - E E E E E E E E TT0_7 TT0_6 TT0_5 TT0_4 TT0_3 TT0_2 TT0_1 TT0_0 E E E E E E E E - - - - F01B6 TPS0 (Timer clock select register 0) - - E - - - - - - - - - - - - F01B8 - - - - F01BA - - - - F01BC - - - - F01BE TO0 (Timer output register 0) - - E - - - - - - - - TO0L - E - - - - - - - - - TOE0 (Timer output enable register 0) - - E - - - - - - - - TOE0L E E - E E E E E E E E TOE0_7 TOE0_6 TOE0_5 TOE0_4 TOE0_3 TOE0_2 TOE0_1 TOE0_0 E E E E E E E E TOL0 (Timer output level register 0) - - E - - - - - - - - TOL0L - E - - - - - - - - - TOM0 (Timer output mode register 0) - - E - - - - - - - - TOM0L - E - - - - - - - - - - - - - F01C0 TCR10 (Timer counter register 10) - - R - - - - - - - - - - - - F01C2 TCR11 (Timer counter register 11) - - R - - - - - - - - 1289 RL78/D1A APPENDIX A NUMBER OF WAIT CYCLES TO ACCESS I/O REGISTERS Specifications in this document are tentative and subject to change. Under development Preliminary document
R01UH0317EJ0004 Rev. 0.04 1290 Feb. 22, 2013 Necessary WAIT I/O register(SFR) name R/W Bit R/W Address READ(MIN.) READ(MAX.) WRITE(MIN.) WRITE(MAX.) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1 8 16 7 6 5 4 3 2 1 0 - - - - F01C4 TCR12 (Timer counter register 12) - - R - - - - - - - - - - - - F01C6 TCR13 (Timer counter register 13) - - R - - - - - - - - - - - - F01C8 TCR14 (Timer counter register 14) - - R - - - - - - - - - - - - F01CA TCR15 (Timer counter register 15) - - R - - - - - - - - - - - - F01CC TCR16 (Timer counter register 16) - - R - - - - - - - - - - - - F01CE TCR17 (Timer counter register 17) - - R - - - - - - - - - - - - F01D0 TMR10 (Timer mode register 10) - - E - - - - - - - - - - - - F01D2 TMR11 (Timer mode register 11) - - E - - - - - - - - - - - - F01D4 TMR12 (Timer mode register 12) - - E - - - - - - - - - - - - F01D6 TMR13 (Timer mode register 13) - - E - - - - - - - - - - - - F01D8 TMR14 (Timer mode register 14) - - E - - - - - - - - - - - - F01DA TMR15 (Timer mode register 15) - - E - - - - - - - - - - - - F01DC TMR16 (Timer mode register 16) - - E - - - - - - - - - - - - F01DE TMR17 (Timer mode register 17) - - E - - - - - - - - - - - - F01E0 - - - - F01E2 - - - - F01E4 - - - - F01E6 - - - - F01E8 - - - - F01EA - - - - F01EC - - - - F01EE TSR10 (Timer status register 10) - - R - - - - - - - - TSR10L - R - - - - - - - - - TSR11 (Timer status register 11) - - R - - - - - - - - TSR11L - R - - - - - - - - - TSR12 (Timer status register 12) - - R - - - - - - - - TSR12L - R - - - - - - - - - TSR13 (Timer status register 13) - - R - - - - - - - - TSR13L - R - - - - - - - - - TSR14 (Timer status register 14) - - R - - - - - - - - TSR14L - R - - - - - - - - - TSR15 (Timer status register 15) - - R - - - - - - - - TSR15L - R - - - - - - - - - TSR16 (Timer status register 16) - - R - - - - - - - - TSR16L - R - - - - - - - - - TSR17 (Timer status register 17) - - R - - - - - - - - TSR17L - R - - - - - - - - - 1290 RL78/D1A APPENDIX A NUMBER OF WAIT CYCLES TO ACCESS I/O REGISTERS Specifications in this document are tentative and subject to change. Under development Preliminary document
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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12.5.3 Master transmission/receptio
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19.2 Configuration of DMA Controlle
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