RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 6 TIMER ARRAY UNIT 6.7.2 Operation as external event counter The timer array unit can be used as an external event counter that counts the number of times the valid input edge (external event) is detected in the TImn pin. When a specified count value is reached, the event counter generates an interrupt. The specified number of counts can be calculated by the following expression. Specified number of counts = Set value of TDRmn + 1 TCRmn operates as a down counter in the event counter mode. When the channel start trigger bit (TSmn) is set to 1, TCRmn loads the value of TDRmn. TCRmn counts down each time the valid input edge of the TImn pin has been detected. When TCRmn = 0000H, TCRmn loads the value of TDRmn again, and outputs INTTMmn. After that, the above operation is repeated. TOmn must not be used because its waveform depends on the external event and irregular. TDRmn can be rewritten at any time. The new value of TDRmn becomes valid during the next count period. TImn pin TSmn Figure 6-55. Block Diagram of Operation as External Event Counter Edge detection Clock selection Trigger selection Remark m: Unit number (m = 0 to 2) n: Channel number (n = 0 to 7) Timer counter (TCRmn) Data register (TDRmn) Interrupt controller Interrupt signal (INTTMmn) R01UH0317EJ0004 Rev. 0.04 409 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-56. Example of Basic Timing of Operation as External Event Counter TSmn TEmn TImn TCRmn TDRmn INTTMmn Remark m: Unit number (m = 0 to 2) 0000H n: Channel number (n = 0 to 7) 3 2 1 0 3 0003H 0002H R01UH0317EJ0004 Rev. 0.04 410 Feb. 22, 2013 2 1 0 2 1 0 4 events 4 events 3 events 2 1
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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12.5.3 Master transmission/receptio
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14.9.1 Message reception ..........
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19.2 Configuration of DMA Controlle
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28.1.1 Programming Environment.....
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