RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 6 TIMER ARRAY UNIT
6.2 Configuration of Timer Array `Unit
The timer array unit includes the following hardware.
Table 6-1. Configuration of Timer Array Unit
Item Configuration
Timer/counter Timer counter register mn (TCRmn)
Register Timer data register mn (TDRmn)
Timer input TI00 to TI07, TI10 to TI17, TI20 to TI27 pins
Timer output TO00 to TO07, TO10 to TO17, TO20 to TO27 pins, output controller
Control registers
Peripheral enable register 0 (PER0)
Timer clock select register m (TPSm)
Timer channel enable status register m (TEm)
Timer channel start register m (TSm)
Timer channel stop register m (TTm)
Timer output enable register m (TOEm)
Timer output register m (TOm)
Timer output level register m (TOLm)
Timer output mode register m (TOMm)
Remark m: Unit number (m = 0 to 2)
n: Channel number (n = 0 to 7)
Timer mode register mn (TMRmn)
Timer status register mn (TSRmn)
Noise filter enable registers 0 to 2 (TNFEN0 to TNFEN2)
Sampling clock select register (TNFSMP0 to TNFSMP2)
Noise filter clock select register (TNFCS0 to TNFCS2)
Timer input select registers 00, 01, 10, 11 (TIS00, TIS01, TIS10, TIS11)
Timer output select registers 00, 01, 10, 11 (TOS00, TOS01, TOS10, TOS11)
Serial communication pin select register 1 (STSEL1)
Timer input select else register (TISELSE)
RTC1Hz pin select register (RTCSEL)
Port mode registers 0, 1, 3, 5 to 9, 13, 14 (PM0, PM1, PM3, PM5 to PM9, PM13, PM14)
Port registers 0, 1, 3, 5 to 9, 13, 14 (P0, P1, P3, P5 to P9, P13, P14)
Figure 6-1, Figure 6-3, and Figure 6-5 show the block diagrams.
R01UH0317EJ0004 Rev. 0.04 318
Feb. 22, 2013