RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 17 SOUND GENERATOR
17.3 Sound Generator Operation
This section explains the details of the Sound Generator.
17.3.1 Generating the tone
The tone signal is generated by the compare match signal of the SG0FH counter value with the value of the SG0FH
buffer, followed by a by-two-divider. At each compare match, the counter is reset to zero.
Remember that the SG0FH counter is clocked by the output of the SG0FL counter.
(1) Updating the frequency buffer values
The values of the frequency buffers can be changed by writing to the associated frequency registers SG0FL and
SG0FH.
Changing the value of the SG0FL (equivalent to SG0F[15:0]) register would also yield a change of the PWM
frequency, i.e. the sound volume. Therefore it is obligatory to write the correct PWM value to SG0PWM before a new
SG0FL value is copied to the frequency buffers.
The following figure shows an example (not to scale).
SG0CLK
SG0FH
Write
SG0PWM
SG0FH
buffer
SG0FH
compare
match
SG0FH
counter
003B H
Figure 17-5. Update Timing of the Frequency Buffers
038 H
003B H
039 H
03A H
If SG0FL is set to 01AEH and a 193 Hz tone is generated, as in the above example, the time span between writing to
the SG0PWM register and updating the buffer can be up to 5.17 ms.
R01UH0317EJ0004 Rev. 0.04 1006
Feb. 22, 2013
0027 H
03B H
000 H
0027 H
001 H