RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER (2) Port mode register 7 (PM7) This register sets input/output of port 7 in 1-bit units. Port 7 alternate function about a PCL output is shown in Table 9-2. When using the P75/PCL pin for clock output and buzzer output, clear the PM75 bit and the output latches of P75 to 0. The PM7 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to FFH. Figure 9-3. Format of Port Mode Register 7 (PM7) Address: FFF27H After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 PM7 1 1 PM75 PM74 PM73 PM72 PM71 PM70 PM7n PM7n pin I/O mode selection (n = 0 to 5) 0 Output mode (output buffer on) 1 Input mode (output buffer off) Table 9-2. Settings of Register, and Output Latch When Using Alternate Function Alternate function Expanded control setting (Register.bit) port Function name I/O PMxx Pxx LCDPFxx Enable function Disable other function P75 TI22 Input 1 x 0 TIS20.5,4 = 00 - TO22 Output 0 0 0 TOS20.5,4 = 00 SGSEL.3 = 1 PCL Output 0 0 0 SGSEL.3 = 0 TOS20.5,4 = 01/10 SI01 Input 1 x 0 STSEL0.4 = 0 - SEG27 Output x x 1 - - R01UH0317EJ0004 Rev. 0.04 493 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER (3) Port mode register 6 (PM6) This register sets input/output of port 6 in 1-bit units. Port 6 alternate function about a PCL output is shown in Table 9-3. When using the P66/PCL pin for clock output and buzzer output, clear the PM66 bit and the output latches of P66 to 0. The PM6 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to FFH. port P66 Figure 9-4. Format of Port Mode Register 6 (PM6) Address: FFF26H After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 PM6 1 PM66 PM65 PM64 PM63 PM62 PM61 PM60 PM6n PM6n pin I/O mode selection (n = 0 to 6) 0 Output mode (output buffer on) 1 Input mode (output buffer off) Table 9-3. Settings of Register, and Output Latch When Using Alternate Function Alternate function PMxx Pxx LCDPFxx Expanded control setting (Register.bit) Function name I/O Enable function Disable other function TI24 Input 1 x TIS21.1,0 = 00 - TO24 Output 0 0 N/A TOS21.1,0 = 00 SGSEL.3 = 0 PCL Output 0 0 SGSEL.3 = 1 TOS21.1,0 = 01/10 R01UH0317EJ0004 Rev. 0.04 494 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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34.2 64-pin products 1276 R5F10CLDx
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RL78/D1A User’s Manual: Hardware
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