RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 12 SERIAL ARRAY UNIT 12.6.4 Stop condition generation After all data are transmitted to or received from the target slave, a stop condition is generated and the bus is released. (1) Processing flow STmn SEmn SOEmn Note SCLr output SDAr output Figure 12-82. Timing Chart of Stop Condition Generation Operation stop SOmn bit manipulation CKOmn bit manipulation Stop condition SOmn bit manipulation Note During the receive operation, the SOEmn bit is set to 0 before receiving the last data. Remark m: Unit number (m = 1), n: Channel number (n = 1), r: IIC number (r = 11) Figure 12-83. Flowchart of Stop Condition Generation Completion of data transmission/data reception Starting generation of stop condition. Writing 1 to STmn bit to clear (SEmn is cleared to 0) Writing 0 to SOEmn bit Writing 0 to SOmn bit Writing 1 to CKOmn bit Wait Writing 1 to SOmn bit End of IIC communication Secure a wait time so that the specifications of I 2 C on the slave side are satisfied. R01UH0317EJ0004 Rev. 0.04 665 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 12 SERIAL ARRAY UNIT 12.6.5 Calculating transfer rate The transfer rate for simplified I 2 C (IIC11) communication can be calculated by the following expressions. (Transfer rate) = {Operation clock (fMCK) frequency of target channel} ÷ (SDRmn[15:9] + 1) ÷ 2 Caution Setting SDRmn[15:9] = 0000000B is prohibited. Setting SDRmn[15:9] = 0000001B or more. Remarks 1. The value of SDRmn[15:9] is the value of bits 15 to 9 of the SDRmn register (0000001B to 1111111B) and therefore is 1 to 127. 2. m: Unit number (m = 1), n: Channel number (n = 1) The operation clock (fMCK) is determined by serial clock select register m (SPSm) and bit 15 (CKSmn) of serial mode register mn (SMRmn). R01UH0317EJ0004 Rev. 0.04 666 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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12.5.3 Master transmission/receptio
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19.2 Configuration of DMA Controlle
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34.2 64-pin products 1276 R5F10CLDx
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34.4 100-pin products 1278 CHAPTER
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