RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 5 CLOCK GENERATOR
5.2 Configuration of Clock Generator
The clock generator includes the following hardware.
Table 5-1. Configuration of Clock Generator
Item Configuration
Control registers Clock operation mode control register (CMC)
System clock control register (CKC)
Clock operation status control register (CSC)
Oscillation stabilization time counter status register (OSTC)
Oscillation stabilization time select register (OSTS)
Peripheral enable registers 0, 1 (PER0, PER1)
Peripheral clock select register(PCKSEL)
Operation speed mode control register (OSMC)
High-speed on-chip oscillator frequency select register (HOCODIV)
High-speed on-chip oscillator trimming register (HIOTRM)
PLL control register (PLLCTL)
PLL status register (PLLSTS)
FMP clock division selection register (MDIV)
Oscillators X1 oscillator
XT1 oscillator
High-speed on-chip oscillator
Low-speed on-chip oscillator
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Feb. 22, 2013