RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 19 DMA CONTROLLER 19.4.2 Transfer mode The following four modes can be selected for DMA transfer by using bits 6 and 5 (DRSn and DSn) of DMA mode control register n (DMCn). DRSn DSn DMA Transfer Mode 0 0 Transfer from SFR of 1-byte data (fixed address) to RAM (address is incremented by +1) 0 1 Transfer from SFR of 2-byte data (fixed address) to RAM (address is incremented by +2) 1 0 Transfer from RAM of 1-byte data (address is incremented by +1) to SFR (fixed address) 1 1 Transfer from RAM of 2-byte data (address is incremented by +2) to SFR (fixed address) By using these transfer modes, up to 1024 bytes of data can be consecutively transferred by using the serial interface, data resulting from A/D conversion can be consecutively transferred, and port data can be scanned at fixed time intervals by using a timer. 19.4.3 Termination of DMA transfer When DBCn = 00H and DMA transfer is completed, the DSTn bit is automatically cleared to 0. An interrupt request (INTDMAn) is generated and transfer is terminated. When the DSTn bit is cleared to 0 to forcibly terminate DMA transfer, DMA byte count register n (DBCn) and DMA RAM address register n (DRAn) hold the value when transfer is terminated. The interrupt request (INTDMAn) is not generated if transfer is forcibly terminated. Remark n: DMA channel number (n = 0 to 3) R01UH0317EJ0004 Rev. 0.04 1037 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 19 DMA CONTROLLER 19.5 Example of Setting of DMA Controller 19.5.1 CSI consecutive transmission A flowchart showing an example of setting for CSI consecutive transmission is shown below. Consecutive transmission of CSI00 or CSI01 (256 bytes) DMA channel 0 is used for DMA transfer. DMA start source: INTCSI00 or INTCSI01 (software trigger (STG0) only for the first start source) Interrupt of CSI00 is specified by IFC03 to IFC00 = 1100B. In case of CSI01, interrupt of CSI01 is specified by IFC03 to IFC00 = 1101B. When INTCSI00 is specified as a DMA start source, transfers FFB00H to FFBFFH (256 bytes) of RAM to FFF10H of the serial data register (SDR00L) of CSI. When INTCSI01 is specified, transfers FFB00H to FFBFFH (256 bytes) of RAM to FFF12H of the serial data register (SDR01L). Remark IFC03 to IFC00: Bits 3 to 0 of DMA mode control registers 0 (DMC0) R01UH0317EJ0004 Rev. 0.04 1038 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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19.2 Configuration of DMA Controlle
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