RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 5 CLOCK GENERATOR 5.2 Configuration of Clock Generator The clock generator includes the following hardware. Table 5-1. Configuration of Clock Generator Item Configuration Control registers Clock operation mode control register (CMC) System clock control register (CKC) Clock operation status control register (CSC) Oscillation stabilization time counter status register (OSTC) Oscillation stabilization time select register (OSTS) Peripheral enable registers 0, 1 (PER0, PER1) Peripheral clock select register(PCKSEL) Operation speed mode control register (OSMC) High-speed on-chip oscillator frequency select register (HOCODIV) High-speed on-chip oscillator trimming register (HIOTRM) PLL control register (PLLCTL) PLL status register (PLLSTS) FMP clock division selection register (MDIV) Oscillators X1 oscillator XT1 oscillator High-speed on-chip oscillator Low-speed on-chip oscillator R01UH0317EJ0004 Rev. 0.04 269 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 5 CLOCK GENERATOR Figure 5-1. Block Diagram of Clock Generator Internal bus FMP clock division selection register (MDIV) System clock control register (CKC) Oscillation stabilization time select register (OSTS) Clock operation status control register (CSC) Clock operation mode control register (CMC) MD IV0 MD IV1 MD IV2 CLS CSS MCS MCM0 OSTS1 OSTS0 OSTS2 MSTOP EXCLK OSCSEL AMPH Standby controller 3 STOP mode 3 X1 oscillation stabilization time counter HALT mode STOP mode signal Normal operation mode MOST 18 MOST 17 MOST 15 MOST 13 MOST 11 MOST 10 MOST 9 MOST 8 High-speed system clock oscillator X1/P121 Oscillation stabilization time counter status register (OSTC) fX Crystal/ceramic oscillation fMX X2/EXCLK /P122 fEX External input clock CAN controller LCD controller/driver Option byte (000C2H) FRQSEL0 to FRQSEL3 High-speed on-chip oscillator CPU, DMA fCLK CAN controller Clock output/ buzzer output fMP/25 fMP/24 Main system clock source selector fMAIN fMP PLL (see Figure 5-2) RTC, Interval timer RTC, Interval timer High-speed on-chip oscillation (24MHz (TYP.)) High-speed on-chip oscillation (32 MHz (TYP.)) Timer array unit 0 Timer array unit 1 Timer array unit 2 Serial array unit 0 Serial array unit 1 LIN-UART0 LIN-UART1 A/D converter Sound generator Stepper motor controller/driver RTC CPU clock and peripheral hardware clock source selection Selector fMP/23 fMP/22 fIH High-speed on-chip oscillation (8 MHz (TYP.)) High-speed on-chip oscillation (16 MHz (TYP.)) fMP/2 Prescaler Option byte (000C0H) WDTON WDSTBYON High-speed on-chip oscillation (4 MHz (TYP.)) R01UH0317EJ0004 Rev. 0.04 270 Feb. 22, 2013 Controller fMP HALT/STOP mode signal Low-speed on-chip oscillator Low-speed on-chip fIL oscillation (15 kHz (TYP.)) Watchdog timer LCD controller/driver RTC Internal timer Clock output/buzzer output LCD controller/driver RTC Interval timer Subsystem clock oscillator fSUB XT1/P123 fXT Crystal oscillation XT2/P124 6 CLS SGEN MTRCEN ADCEN TAU0 EN TAU1 EN TAU2 EN SAU0 EN SAU1 EN LIN0 EN LIN1 EN RTC EN HIOTRM5 HIOTRM4 HIOTRM3 HIOTRM2 HIOTRM1 HIOTRM0 XTSTOP HIOSTOP HOCODIV2 HOCODIV1 HOCODIV0 OSCSELS AMPHS0 AMPHS1 Peripheral enable register 1 (PER1) Peripheral enable register 0 (PER0) High-speed on-chip oscillator trimming register(HIOTRM) Clock operation status control register (CSC) High-speed on-chip oscillator frequency select register (HOCODIV) Clock operation mode control register (CMC) Internal bus (Remark is listed on the next page after next.)
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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RL78/D1A User’s Manual: Hardware
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