RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 6 TIMER ARRAY UNIT 6.1.3 LIN-bus supporting function (Channel 3 of the timer array unit 0, channels 1 and 4 of the timer array unit 1, and channel 0 of the timer array unit 2 only) (1) Detection of wakeup signal The timer starts counting at the falling edge of a signal input to the serial data input pin (LRxD0, LRxD1) of LIN- UART 0, 1 and the count value of the timer is captured at the rising edge. In this way, a low-level width can be measured. If the low-level width is greater than a specific value, it is recognized as a wakeup signal. (2) Measurement of pulse width of sync field After a sync break field is detected, the low-level width and high-level width of the signal input to the serial data input pin (LRxD0, LRxD1) of LIN-UART0, 1 are measured. From the bit interval of the sync field measured in this way, a baud rate is calculated. R01UH0317EJ0004 Rev. 0.04 317 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 6 TIMER ARRAY UNIT 6.2 Configuration of Timer Array `Unit The timer array unit includes the following hardware. Table 6-1. Configuration of Timer Array Unit Item Configuration Timer/counter Timer counter register mn (TCRmn) Register Timer data register mn (TDRmn) Timer input TI00 to TI07, TI10 to TI17, TI20 to TI27 pins Timer output TO00 to TO07, TO10 to TO17, TO20 to TO27 pins, output controller Control registers Peripheral enable register 0 (PER0) Timer clock select register m (TPSm) Timer channel enable status register m (TEm) Timer channel start register m (TSm) Timer channel stop register m (TTm) Timer output enable register m (TOEm) Timer output register m (TOm) Timer output level register m (TOLm) Timer output mode register m (TOMm) Remark m: Unit number (m = 0 to 2) n: Channel number (n = 0 to 7) Timer mode register mn (TMRmn) Timer status register mn (TSRmn) Noise filter enable registers 0 to 2 (TNFEN0 to TNFEN2) Sampling clock select register (TNFSMP0 to TNFSMP2) Noise filter clock select register (TNFCS0 to TNFCS2) Timer input select registers 00, 01, 10, 11 (TIS00, TIS01, TIS10, TIS11) Timer output select registers 00, 01, 10, 11 (TOS00, TOS01, TOS10, TOS11) Serial communication pin select register 1 (STSEL1) Timer input select else register (TISELSE) RTC1Hz pin select register (RTCSEL) Port mode registers 0, 1, 3, 5 to 9, 13, 14 (PM0, PM1, PM3, PM5 to PM9, PM13, PM14) Port registers 0, 1, 3, 5 to 9, 13, 14 (P0, P1, P3, P5 to P9, P13, P14) Figure 6-1, Figure 6-3, and Figure 6-5 show the block diagrams. R01UH0317EJ0004 Rev. 0.04 318 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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6.8 Operation of Plural Channels of
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34.2 64-pin products 1276 R5F10CLDx
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RL78/D1A User’s Manual: Hardware
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