RL78/D1A User's Manual: Hardware - Renesas

Operation is resumed (on the next page).
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 6 TIMER ARRAY UNIT
TAU
default
setting
Channel
default
setting
Operation
start
Figure 6-85. Operation Procedure When Multiple PWM Output Function Is Used (1/2)
Software Operation Hardware Status
Sets the TAU0EN bit, TAU1EN bit of the PER0 register
to 1.
Sets the TPSm register.
Determines clock frequencies of CKm0 to CKm3.
Sets the TMRmn, TMRmp, and TMRmq registers of
each channel to be used (determines operation mode of
channels).
An interval (period) value is set to the TDRmn register of
the master channel, and a duty factor is set to the
TDRmp and TDRmq registers of the slave channel.
Sets slave channel.
The TOMmp and TOMmq bits of the TOMm register
are set to 1 (combination operation mode).
Clears the TOLmp and TOLmq bits to 0.
Sets the TOmp and TOmq bits and determines default
level of the TOmp and TOmq outputs.
Sets TOEmp and TOEmq to 1 and enables operation
of TOmp and TOmq.
Clears the port register and port mode register to 0.
Sets TOEmp and TOEmq (slave) to 1 (only when
operation is resumed).
The TSmn bit (master), and TSmp and TSmq (slave) bits
of the TSm register are set to 1 at the same time.
The TSmn, TSmp, and TSmq bits automatically return
to 0 because they are trigger bits.
Power-off status
(Clock supply is stopped and writing to each register is
disabled.)
Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
Channel stops operating.
(Clock is supplied and some power is consumed.)
The TOmp and TOmq pins go into Hi-Z output state.
The TOmp and TOmq default setting levels are output
when the port mode register is in output mode and the port
register is 0.
TOmp or TOmq does not change because channel stops
operating.
The TOmp and TOmq pins output the TOmp and TOmq
set levels.
TEmn = 1, TEmp, TEmq = 1
When the master channel starts counting, INTTMmn is
generated. Triggered by this interrupt, the slave channel
also starts counting.
R01UH0317EJ0004 Rev. 0.04 454
Feb. 22, 2013