RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 22 RESET FUNCTION
Table 22-2. Hardware Statuses After Reset Acknowledgment (2/7)
Hardware Status After Reset
Note 1
Acknowledgment
Timer input select else register (TISELSE) 00H
Sound generator pin select register (SGSEL) 00H
Timer output select register 00, 01, 10, 11, 20, 21 (TOS00, TOS01, TOS10, TOS11, TOS20, TOS21) 00H
Timer array unit Noise filter enable register for each channel of TAU unit0 to 2 BCD correction
result register ( TNFEN0BCDAJ to TNFEN2)
00H
Sampling clock select of noise filter for unit0 to 2 (2 set) (TNFSMP0, TNFSMP1,
TNFSMP2)
00H
Noise filter clock select register for each channel of TAU unit0 to 2 (TNFCS0,
TNFCS1, TNFCS2)
00H
Real-time clock
Second count register (SEC) 00H
Minute count register (MIN) 00H
Hour count register (HOUR) 12H
Week count register (WEEK) 00H
Day count register (DAY) 01H
Month count register (MONTH) 01H
Year count register (YEAR) 00H
Watch error correction register (SUBCUD, SUBCUDW) 00H, 0000H
Alarm minute register (ALARMWM) 00H
Alarm hour register (ALARMWH) 12H
Alarm week register ALARMWW) 00H
Control register 0 (RTCC0) 00H
Control register 1 (RTCC1) 00H
RTC clock selection register (RTCCL) 00H
RTC1Hz pin select register (RTCSEL) 00H
Interval timer Interval timer control register (ITMC) 7FFFH
Clock output/buzzer
output controller
Clock output select register 0 (CKS0) 00H
Note 2
Watchdog timer Watchdog timer enable register (WDTE) 1AH/9AH
A/D converter
10-bit A/D conversion result register (ADCR) 0000H
8-bit A/D conversion result register (ADCRH) 00H
Mode registers 0 to 2 (ADM0 to ADM2) 00H
Conversion result comparison upper limit setting register (ADUL) FFH
Conversion result comparison lower limit setting register (ADLL) 00H
A/D test register (ADTES) 00H
Analog input channel specification register (ADS) 00H
A/D port configuration register (ADPC) 00H
Notes 1. During reset signal generation or oscillation stabilization time wait, only the PC contents among the hardware
statuses become undefined. All other hardware statuses remain unchanged after reset.
2. The reset value of WDTE is determined by the option byte setting.
Remark The special function register (SFR) mounted depend on the product. See 3.1.4 Special function registers
(SFRs) and 3.1.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers).
R01UH0317EJ0004 Rev. 0.04 1098
Feb. 22, 2013