RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF)
13.5.9 BF reception mode select function
A mode for BF (break field) reception, which can be selected by using the LIN-UART operation mode selection bits
(UFnMD1, UFnMD0), is provided.
(1) Normal UART mode (UFnMD1 and UFnMD0 = 00B)
In normal UART mode (UFnMD1 and UFnMD0 = 00B), a new BF is only recognized when the system is waiting for
a BF to be successfully received (UFnBRF = 1).
If the system is not waiting for a BF to be successfully received (UFnBRF = 0), framing or overrun errors are
detected at the data’s stop bit position (bit 10) (see Figure 13-42). If an overrun error has not occurred, the
received data is stored in the UFnRX register. If the system is waiting for a BF to be successfully received
(UFnBRF = 1), framing or overrun errors are not detected and the received data is not stored in the UFnRX register.
If UFnBRF = 0 and reception is stopped when data or the BF stop bit is transmitted, the data consistency error
interrupt is issued and the flag is changed when transmission of the bit following the stop bit starts (see 13.5.8 (2)).
If reception is in progress when the stop bit is transmitted, the data consistency error interrupt is issued and the
flag is changed when transmission of the stop bit starts (see 13.5.8 (1)). On the other hand, if UFnBRF = 1 and
reception is stopped when the stop bit is transmitted, the data consistency error interrupt is issued and the flag is
changed when transmission of the bit following the stop bit starts (see Figure 13-43) and if reception is in progress
when the stop bit is transmitted, the data consistency error interrupt is issued and the flag is changed when the
rising edge of the input data following the stop bit is detected (see Figure 13-44).
LRxDn input
Data sampling
UFnFE flag,
UFnOVE flag
INTLSn
Caution The successful BF reception flag (UFnBSF) is not set in normal UART mode.
Figure 13-40. Timing of Judging Framing or Overrun Error in Normal UART Mode
Start
bit
D0 D1 D4 D5 D6 D7
R01UH0317EJ0004 Rev. 0.04 740
Feb. 22, 2013
Stop
bit