RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 21 STANDBY FUNCTION
(2) HALT mode release
The HALT mode can be released by the following two sources.
(a) Release by unmasked interrupt request
When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgment is
enabled, vectored interrupt servicing is carried out. If interrupt acknowledgment is disabled, the next address
instruction is executed.
High-speed system clock,
internal high-speed oscillation clock,
or subsystem clock
Figure 21-3. HALT Mode Release by Interrupt Request Generation
Standby
release signal Note1
Status of CPU
Operating mode
HALT
instruction
Interrupt
request
HALT mode
Oscillation
Wait Note2
Operating mode
Notes 1. For details of the standby release signal, see Figure 20-1. Basic Configuration of Interrupt Function.
2. Wait time for HALT mode release
When vectored interrupt servicing is carried out
Main system clock: 15 to 16 clock
Subsystem clock (RTCLPC = 0): 10 to 11 clock
Subsystem clock (RTCLPC = 1): 11 to 12 clock
When vectored interrupt servicing is not carried out
Main system clock: 9 to 10 clock
Subsystem clock (RTCLPC = 0): 4 to 5 clock
Subsystem clock (RTCLPC = 1): 5 to 6 clock
Remark The broken lines indicate the case when the interrupt request which has released the standby mode is
acknowledged.
R01UH0317EJ0004 Rev. 0.04 1081
Feb. 22, 2013