RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF) LTxDn pin LRxDn pin INTLSn INTLRn UFnHDC flag UFnBUC flag UFnNO bit UFnRRQ bit UFnTRQ bit UFnBUL3 to UFnBUL0 bits (write) UFnBUL3 to UFnBUL0 bits (read) Figure 13-54. LIN Communication Automatic Baud Rate Mode (Response Reception) “H” BF SF PID data data CSF UFnID register PID “L” “L” “L” Sets UFnCLHDC bit to 1 R01UH0317EJ0004 Rev. 0.04 755 Feb. 22, 2013 Clear Set Clear 0 1 (m−1) m Sets UFnRRQ bit to 1 m Wait for next successful BF reception Sets UFnCLBUC bit to 1 An example of how reception results are stored into a buffer when 8-byte data is received (UFnBUL3 to UFnBUL0 = 9) and when 3-byte data is received (UFnBUL3 to UFnBUL0 = 3) are shown below. (1) When 8-byte data is received (UFnBUL3 to UFnBUL0 = 9) (2) When 3-byte data is received (UFnBUL3 to UFnBUL0 = 3) Reception results Reception results UFnBUF8 Checksum UFnBUF8 UFnBUF7 Data7 UFnBUF7 UFnBUF6 Data6 UFnBUF6 UFnBUF5 Data5 UFnBUF5 UFnBUF4 Data4 UFnBUF4 UFnBUF3 Data3 UFnBUF3 Checksum UFnBUF2 Data2 UFnBUF2 Data2 UFnBUF1 Data1 UFnBUF1 Data1 UFnBUF0 Data0 UFnBUF0 Data0 Caution When UARTF is being used with the auto checksum feature enabled (UFnACE = 1), the checksum data is not stored in a buffer. Remark n = 0, 1
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF) LTxDn pin LRxDn pin INTLSn INTLRn UFnHDC flag UFnBUC flag UFnNO bit UFnRRQ bit UFnTRQ bit UFnBUL3 to UFnBUL0 bits (write) UFnBUL3 to UFnBUL0 bits (read) Figure 13-55. LIN Communication Automatic Baud Rate Mode (Response Transmission) Clear Set data data CSF BF SF PID data data CSF UFnID register PID INTLTn “L” “L” “L” Sets UFnCLHDC bit to 1 R01UH0317EJ0004 Rev. 0.04 756 Feb. 22, 2013 Clear 0 1 2 m Sets UFnTRQ bit to 1 m Wait for next successful BF reception Sets UFnCLBUC bit to 1 Examples of the buffer settings and the status of the buffer after 8 bytes of data have been transmitted (UFnBUL3 to UFnBUL0 = 9) and after 3 bytes of data have been transmitted (UFnBUL3 to UFnBUL0 = 3) are shown below. (1) When 8-byte data is transmitted (UFnBUL3 to UFnBUL0 = 9) Buffer setting Buffer status UFnBUF8 TX Checksum RX Checksum UFnBUF7 Data7 Data7 UFnBUF6 Data6 Data6 UFnBUF5 Data5 Data5 UFnBUF4 Data4 Data4 UFnBUF3 Data3 Data3 UFnBUF2 Data2 Data2 UFnBUF1 Data1 Data1 UFnBUF0 Data0 Data0
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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