RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 14 CAN CONTROLLER 14.2.2 Frame types The following four types of frames are used in the CAN protocol. Table 14-2. Frame Types Frame Type Description Data frame Frame used to transmit data Remote frame Frame used to request a data frame Error frame Frame used to report error detection Overload frame Frame used to delay the next data frame or remote frame (1) Bus value The bus values are divided into dominant and recessive. - Dominant level is indicated by logical 0. - Recessive level is indicated by logical 1. - When a dominant level and a recessive level are transmitted simultaneously, the bus value becomes dominant level. 14.2.3 Data frame and remote frame (1) Data frame A data frame is composed of seven fields. R D Figure 14-3. Data Frame Data frame Remark D: Dominant = 0 R: Recessive = 1 Interframe space End of frame (EOF) ACK field CRC field Data field Control field Arbitration field Start of frame (SOF) R01UH0317EJ0004 Rev. 0.04 787 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 14 CAN CONTROLLER (2) Remote frame A remote frame is composed of six fields. R D Figure 14-4. Remote Frame Remote frame Interframe space End of frame (EOF) ACK field CRC field Control field Arbitration field Start of frame (SOF) Remarks 1. The data field is not transferred even if the control field’s data length code is not “0000B”. 2. D: Dominant = 0 R: Recessive = 1 (3) Description of fields Start of frame (SOF) The start of frame field is located at the start of a data frame or remote frame. R D Figure 14-5. Start of Frame (SOF) (Interframe space or bus idle) Start of frame (Arbitration field) Remark D: Dominant = 0 R: Recessive = 1 R01UH0317EJ0004 Rev. 0.04 788 Feb. 22, 2013 1 bit If dominant level is detected in the bus idle state, a hard-synchronization is performed (the current TQ is assigned to be the SYNC segment). If dominant level is sampled at the sample point following such a hard-synchronization, the bit is assigned to be a SOF. If recessive level is detected, the protocol layer returns to the bus idle state and regards the preceding dominant pulse as a disturbance only. No error frame is generated in such case.
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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19.2 Configuration of DMA Controlle
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