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RL78/D1A User's Manual: Hardware - Renesas

RL78/D1A User's Manual: Hardware - Renesas

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Under development<br />

Preliminary document<br />

Specifications in this document are tentative and subject to change.<br />

<strong>RL78</strong>/<strong>D1A</strong> CHAPTER 12 SERIAL ARRAY UNIT<br />

(6) Serial status register mn (SSRmn)<br />

SSRmn is a register that indicates the communication status and error occurrence status of channel n. The errors<br />

indicated by this register are a framing error, parity error, and overrun error.<br />

SSRmn can be read by a 16-bit memory manipulation instruction.<br />

The lower 8 bits of SSRmn can be set with an 8-bit memory manipulation instruction with SSRmnL.<br />

Reset signal generation clears this register to 0000H.<br />

Figure 12-11. Format of Serial Status Register mn (SSRmn) (1/2)<br />

Address: F0100H, F0101H (SSR00), F0102H, F0103H (SSR01), After reset: 0000H R<br />

F0130H, F0131H (SSR10), F0132H, F0133H (SSR11)<br />

Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />

SSRmn 0 0 0 0 0 0 0 0 0 TSF<br />

mn<br />

TSF<br />

mn<br />

0 When the STmn and SSmn bits are set to “1”<br />

Communication is not under execution.<br />

1 Communication is under execution.<br />

R01UH0317EJ0004 Rev. 0.04 574<br />

Feb. 22, 2013<br />

BFF<br />

mn<br />

Communication status indication flag of channel n<br />

0 0 0 PEF<br />

mn<br />

Because this flag is an updating flag, it is automatically cleared when the communication operation is completed.<br />

This flag is cleared also when the STmn/SSmn bit is set to 1.<br />

BFF<br />

mn<br />

0 When the STmn and SSmn bits are set to “1”<br />

Valid data is not stored in the SDRmn register.<br />

1 Valid data is stored in the SDRmn register.<br />

Buffer register status indication flag of channel n<br />

This is an updating flag. It is automatically cleared when transfer from the SDRmn register to the shift register is<br />

completed. During reception, it is automatically cleared when data has been read from the SDRmn register. This<br />

flag is cleared also when the STmn/SSmn bit is set to 1.<br />

This flag is automatically set if transmit data is written to the SDRmn register when the TXEmn bit of the SCRmn<br />

register = 1 (transmission or reception mode in each communication mode). It is automatically set if receive data is<br />

stored in the SDRmn register when the RXEmn bit of the SCRmn register = 1 (transmission or reception mode in<br />

each communication mode). It is also set in case of a reception error.<br />

If data is written to the SDRmn register when BFFmn = 1, the transmit/receive data stored in the register is<br />

discarded and an overrun error (OVFmn = 1) is detected.<br />

Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 1)<br />

OVF<br />

mn

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