RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 14 CAN CONTROLLER 14.9 Message Reception 14.9.1 Message reception In all the operation modes, the complete message buffer area is analyzed to find a suitable buffer to store a newly received message. All message buffers satisfying the following conditions are included in that evaluation (RX-search process). - Used as a message buffer (MA0 bit of C0MCONFm register set to 1B.) - Set as a receive message buffer (MT [2:0] bits of C0MCONFm register set to 001B, 010B, 011B, 100B, or 101B.) - Ready for reception (RDY bit of C0MCTRLm register set to 1.) When two or more message buffers of the CAN module receive a message, the message is stored according to the priority explained below. The message is always stored in the message buffer with the highest priority, not in a message buffer with a low priority. For example, when an unmasked receive message buffer and a receive message buffer linked to mask 1 have the same ID, the received message is not stored in the message buffer linked to mask 1, even if that message buffer has not received a message and a message has already been received in the unmasked receive message buffer. In other words, when a condition has been set to store a message in two or more message buffers with different priorities, the message buffer with the highest priority always stores the message; the message is not stored in message buffers with a lower priority. This also applies when the message buffer with the highest priority is unable to receive and store a message (i.e., when DN = 1 indicating that a message has already been received, but rewriting is disabled because OWS = 0). In this case, the message is not actually received and stored in the candidate message buffer with the highest priority, but neither is it stored in a message buffer with a lower priority. Priority Storing Condition If Same ID is Set 1 (high) Unmasked message buffer DN = 0 2 Message buffer linked to mask 1 DN = 0 3 Message buffer linked to mask 2 DN = 0 4 Message buffer linked to mask 3 DN = 0 5(low) Message buffer linked to mask 4 DN = 0 Remark m = 0 to 15 DN = 1 and OWS = 1 DN = 1 and OWS = 1 DN = 1 and OWS = 1 DN = 1 and OWS = 1 DN = 1 and OWS = 1 R01UH0317EJ0004 Rev. 0.04 885 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 14 CAN CONTROLLER 14.9.2 Receive Data Read To keep data consistency when reading CAN message buffers, perform the data reading according to Figure 14-76 to 14-78. During message reception, the CAN module sets DN of the C0MCTRLm register two times: at the beginning of the storage process of data to the message buffer, and again at the end of this storage process. During this storage process, the MUC bit of the C0MCTRLm register of the message buffer is set. (Refer to Figure 14-55.) The receive history list is also updated just before the storage process. In addition, during storage process (MUC = 1), the RDY bit of the C0MCTRLm register of the message buffer is locked to avoid the coincidental data WR by CPU. Note the storage process may be disturbed (delayed) when the CPU accesses the message buffer. CAN std ID format DN MUC CINTS1 INTREC1 SOF (1) Figure 14-55. DN and MUC Bit Setting Period (for Standard ID Format) ID R0 IDE RTR Operation of the CAN contoroller Remark m = 0 to 15 DLC DATA0-DATA7 CRC ACK EOF (11) (1) (1) (1) (4) (0-64) (16) (2) Message Store MDATA,MDLC.MIDx- > MBUF Recessive Dominant R01UH0317EJ0004 Rev. 0.04 886 Feb. 22, 2013 (7) IFS Set DN & MUC at the same time Set DN & clear MUC at the same timing
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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