RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-70. Flowchart of Slave Transmission/Reception (in Continuous Transmission/Reception Mode) Writing 1 to MDmn0 bit No Yes Starting CSI communication Setting SAU1EN and SAU0EN bits of PER0 register to 1 Setting transfer rate by SPSm register SMRmn, SCRmn: Setting communication SDRmn[15:9]: Setting 0000000B SOm, SOEm: Setting output Port manipulation Writing 1 to SSmn bit Writing transmit data to SDRmn register Buffer empty interrupt generated? Yes Reading receive data to SDRmn register Communication data exists? No Clearing 0 to MDmn0 bit TSFmn = 1? Yes Transfer end interrupt generated? Yes Reading receive data to SDRmn register Communication continued? No Writing 1 to STmn bit Clearing SAU1EN and SAU0EN bits of PER0 register to 0 End of communication Perform initial setting when SEmn = 0. Select the buffer empty interrupt. Cautions 1. After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more clocks have elapsed. 2. Be sure to set transmit data to the SDRpL register before the clock from the master is started. Remark to in the figure correspond to to in Figure 12-69 Timing Chart of Slave Transmission/Reception (in Continuous Transmission/Reception Mode). R01UH0317EJ0004 Rev. 0.04 645 Feb. 22, 2013 No No Yes
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 12 SERIAL ARRAY UNIT 12.5.7 Calculating transfer clock frequency The transfer clock frequency for 3-wire serial I/O (CSI00, CSI01, CSI10) communication can be calculated by the following expressions. (1) Master (2) Slave (Transfer clock frequency) [Hz] = {Operation clock (fMCK) frequency of target channel} ÷ (SDRmn[15:9] + 1) 2 (Transfer clock frequency) [Hz] = {Frequency of serial clock (fSCK) supplied by master} Note Note The permissible maximum transfer clock frequency is fMCK/6. Remarks 1. The value of SDRmn[15:9] is the value of bits 15 to 9 of the SDRmn register (0000000B to 1111111B) and therefore is 0 to 127. 2. m: Unit number (m = 0, 1), n: Channel number (n = 0, 1) The operation clock (fMCK) is determined by serial clock select register m (SPSm) and bit 15 (CKSmn) of serial mode register mn (SMRmn). R01UH0317EJ0004 Rev. 0.04 646 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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12.5.3 Master transmission/receptio
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19.2 Configuration of DMA Controlle
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34.2 64-pin products 1276 R5F10CLDx
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34.4 100-pin products 1278 CHAPTER
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RL78/D1A User’s Manual: Hardware
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