RL78/D1A User's Manual: Hardware - Renesas

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Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 11 A/D CONVERTER
11.6.10 Hardware trigger wait mode (select mode, one-shot conversion mode)
In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the
hardware trigger standby status.
If a hardware trigger is input while in the hardware trigger standby status, A/D conversion is performed on the
analog input specified by the analog input channel specification register (ADS). The ADCS bit of the ADM0
register is automatically set to 1 according to the hardware trigger input.
When A/D conversion ends, the conversion result is stored in the A/D conversion result register (ADCR, ADCRH),
and the A/D conversion end interrupt request signal (INTAD) is generated.
After A/D conversion ends, the ADCS bit is automatically cleared to 0, and the A/D converter enters the stop
status.
If a hardware trigger is input during conversion operation, the current A/D conversion is interrupted, and
conversion restarts. The partially converted data is discarded.
When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D
conversion is interrupted, and A/D conversion is performed on the analog input respecified by the ADS register.
The partially converted data is discarded.
When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and
conversion restarts. The partially converted data is initialized.
When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, the system
enters the hardware trigger standby status, and the A/D converter enters the stop status. When ADCE = 0,
inputting a hardware trigger is ignored and A/D conversion does not start.
Figure 11-28. Example of Hardware Trigger Wait Mode (Select Mode, One-Shot Conversion Mode) Operation
Timing
ADCE
Hardware
trigger
ADCR,
ADCRH
INTAD
ADCE is set to 1.
A hardware trigger
A hardware trigger is
generated during A/D
is generated.
conversion operation.
The trigger is not Trigger ADCS is automatically
standby
acknowledged. status cleared to 0 after
conversion ends.
ADCS
ADS is rewritten
during A/D conversion
operation (from ANI0
to ANI1).
ADCS is overwritten
with 1 during A/D
conversion operation.
ADCS is cleared
to 0 during A/D
conversion
operation.
ADS
Data 0
(ANI0)
Data 1
(ANI1)
A/D
conversion
status
Stop status Data 0
(ANI0)
A/D conversion
ends.
Stop Data 0
status (ANI0)
Conversion is
interrupted
and restarts.
Data 0 Stop
(ANI0) status
Data 0
(ANI0)
Conversion is
interrupted
and restarts.
Data 1 Stop
(ANI1) status
Data 1
(ANI1)
Conversion is
interrupted
and restarts.
Data 1 Stop
(ANI1) status
Data 1
(ANI1)
Conversion is
interrupted.
Stop status
Data 0
(ANI0)
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Data 0
(ANI0)
Data 1
(ANI1)
Data 1
(ANI1)
Trigger
standby
status