RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF)
(7) LIN-UARTn status register (UFnSTR)
The UFnSTR register is a 16-bit register that displays the LIN-UARTn communication status and reception error
contents.
This register is read-only, in 16-bit units.
Reset sets this register to 0000H.
Caution Flags other than the UFnTSF and UFnRSF flags are retained until the target bits of the LIN-
UARTn status clear register (UFnSTC) are written (“1”) and then cleared. To clear a status flag,
use a 16-bit manipulation instruction to write (“1”) and clear the target bits of the LIN-UARTn
status clear register (UFnSTC).
Figure 13-7. Format of LIN-UARTn Status Register (UFnSTR) (1/6)
Address: F0246H, F0247H (UF0STR), F0266H, F0267H (UF1STR) After reset: 0000H R
15 14 13 12 11 10 9 8
UFnSTR 0 UFnIPE UFnCSE UFnRPE UFnHDC UFnBUC UFnIDM UFnEBD
(n = 0, 1) 7 6 5 4 3 2 1 0
UFnTSF UFnRSF 0 UFnBSF UFnDCE UFnPE UFnFE UFnOVE
UFnIPE ID parity error flag
0 No ID parity error has occurred.
1 An ID parity error has occurred.
Parity of received PID is incorrect
The UFnIPE bit is a flag indicating the check status by the ID parity check function. It becomes
“1”, if the parity of the received PID is incorrect when in automatic baud rate mode (UFnMD1,
UFnMD0 = 11B). See 13.7.3 ID parity check function for details.
The UFnIPE bit will not be cleared until “1” is written to the UFnCLIPE bit of the UFnSTC register,
because the UFnIPE bit is a cumulative flag. It will not be set if the ID parity check function has
been disabled (UFnIPCS = 0).
R01UH0317EJ0004 Rev. 0.04 695
Feb. 22, 2013