RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 6 TIMER ARRAY UNIT Master channel (one-count mode) Operation clock TSmn TImn pin Slave channel (one-count mode) Operation clock Figure 6-76. Block Diagram of Operation as One-Shot Pulse Output Function CKm3 CKm2 CKm1 CKm0 CKm3 CKm2 CKm1 CKm0 Edge detection Clock selection Trigger selection Clock selection Trigger selection Timer counter (TCRmn) Data register (TDRmn) Timer counter (TCRmp) Data register (TDRmp) Interrupt controller Output controller Interrupt controller Remark m: Unit number (m = 0 to 2), n: Master channel number, p: Slave channel number (p = n + 1) Interrupt signal (INTTMmn) TOmp pin Interrupt signal (INTTMmp) R01UH0317EJ0004 Rev. 0.04 439 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-77. Example of Basic Timing of Operation as One-Shot Pulse Output Function Master channel Slave channel TSmn TEmn TImn TCRmn TDRmn TOmn INTTMmn TSmp TEmp TCRmp TDRmp TOmp INTTMmp FFFFH 0000H FFFFH 0000H R01UH0317EJ0004 Rev. 0.04 440 Feb. 22, 2013 a b a+2 b a+2 b Remark m: Unit number (m = 0 to 2), n: Master channel number, p: Slave channel number (p = n + 1)
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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12.5.3 Master transmission/receptio
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14.9.1 Message reception ..........
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19.2 Configuration of DMA Controlle
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28.1.1 Programming Environment.....
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RL78/D1A User’s Manual: Hardware
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