RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 22 RESET FUNCTION Multiplier & divider, multiply-accumulator Table 22-2. Hardware Statuses After Reset Acknowledgment (7/7) Hardware Status After Reset Multiplication/division data register A (MDAL, MDAH) 0000H Multiplication/division data register B (MDBL, MDBH) 0000H Multiplication/division data register C (MDCL, MDCH) 0000H Multiplication/division control register (MDUC) 00H Note 1 Acknowledgment Reset function Note 2 Reset control flag register (RESF) Undefined Note 2 CLM reset control flag register (RESFCLM) 00H POR reset confirm register (POCRES) 00H Voltage detector Voltage detection register (LVIM) Note 2 00H Voltage detection level register (LVIS) Notes 2, 3 00H/01H/81H Safety functions Flash memory CRC control register (CRC0CTL) 00H Flash memory CRC operation result register (PGCRCL) 0000H CRC input register (CRCIN) 00H CRC data register (CRCD) 0000H Invalid memory access detection control register (IAWCTL) 00H RAM parity error control register (RPECTL) 00H Specific register manipulation protection register (GUARD) 00H Flash memory Data flash control register (DFLCTL) 00H BCD correction circuit BCD correction result register (BCDADJ) Undefined Notes 1. During reset signal generation or oscillation stabilization time wait, only the PC contents among the hardware statuses become undefined. All other hardware statuses remain unchanged after reset. 2. These values vary depending on the reset source. Reset Source Register RESF RESFCLM CLKRF bit RESET Input Reset by POR Reset by Execution of Illegal Instruction Reset by WDT TRAP bit Cleared Cleared Set (1) Held WDTRF bit (0) (0) Held Set (1) Reset by RAM parity error Reset by illegalmemory access Reset by LVD Reset by clock monitor R01UH0317EJ0004 Rev. 0.04 1103 Feb. 22, 2013 Held RPERF bit Held Set (1) Held IAWRF bit Held Set (1) LVIRF bit Held Set (1) Held Held Held Set (1) LVIM LVISEN bit Cleared (0) Cleared (0) Cleared (0) Cleared (0) Cleared (0) Cleared (0) Held Cleared (0) LVIOMSK bit LVIF bit Held Held Held Held Held Held Held Held LVIS Cleared Cleared Cleared Cleared Cleared Cleared Held Cleared (00H/01H/ (00H/01H/ (00H/01H/ (00H/01H/ (00H/01H/ (00H/01H/ (00H/01H/ 81H) 81H) 81H) 81H) 81H) 81H) 81H) 3. The generation of reset signal other than an LVD reset sets as follows. • When option byte LVIMDS1, LVIMDS0 = 1, 0: 00H • When option byte LVIMDS1, LVIMDS0 = 1, 1: 81H • When option byte LVIMDS1, LVIMDS0 = 0, 1: 01H Remark The special function register (SFR) mounted depend on the product. See 3.1.4 Special function registers (SFRs) and 3.1.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers).
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 22 RESET FUNCTION 22.1 Register for Confirming Reset Source Many internal reset generation sources exist in the RL78/D1A. The reset control flag register (RESF) is used to store which source has generated the reset request. The RESF register can be read by an 8-bit memory manipulation instruction. RESET input, reset by power-on-reset (POR) circuit, and reading the RESF register clear TRAP, WDTRF, RPERF, IAWRF, and LVIRF flags. Address: FFFA8H After reset: 00H Note 1 R Figure 22-5. Format of Reset Control Flag Register (RESF) Symbol 7 6 5 4 3 2 1 0 RESF TRAP 0 0 WDTRF 0 RPERF IAWRF LVIRF Note 2 TRAP Internal reset request by execution of illegal instruction 0 Internal reset request is not generated, or the RESF register is cleared. 1 Internal reset request is generated. WDTRF Internal reset request by watchdog timer (WDT) 0 Internal reset request is not generated, or the RESF register is cleared. 1 Internal reset request is generated. RPERF Internal reset request by RAM parity 0 Internal reset request is not generated, or the RESF register is cleared. 1 Internal reset request is generated. IAWRF Internal reset request by illegal-memory access 0 Internal reset request is not generated, or the RESF register is cleared. 1 Internal reset request is generated. LVIRF Internal reset request by voltage detector (LVD) 0 Internal reset request is not generated, or the RESF register is cleared. 1 Internal reset request is generated. Notes 1. The value after reset varies depending on the reset source. 2. The illegal instruction is generated when instruction code FFH is executed. Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug emulator. Cautions 1. Do not read data by a 1-bit memory manipulation instruction. 2. An instruction code fetched from RAM is not subject to parity error detection while it is being executed. However, the data read by the instruction is subject to parity error detection. 3. Because the RL78’s CPU executes lookahead due to the pipeline operation, the CPU might read an uninitialized RAM area that is allocated beyond the RAM used, which causes a RAM parity error. Therefore, when enabling RAM parity error resets (RPERDIS = 1), be sure to initialize the used RAM area + 10 bytes. The status of the RESF register when a reset request is generated is shown in Table 22-3. R01UH0317EJ0004 Rev. 0.04 1104 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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