RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 20 INTERRUPT FUNCTIONS Figure 20-10. Examples of Multiple Interrupt Servicing (2/2) Example 3. Multiple interrupt servicing does not occur because interrupts are not enabled INTxx (PR = 11) Main processing INTxx servicing INTyy servicing EI 1 instruction execution IE = 0 INTyy (PR = 00) IE = 1 R01UH0317EJ0004 Rev. 0.04 1071 Feb. 22, 2013 IE = 0 IE = 1 Interrupts are not enabled during servicing of interrupt INTxx (EI instruction is not issued), therefore, interrupt request INTyy is not acknowledged and multiple interrupt servicing does not take place. The INTyy interrupt request is held pending, and is acknowledged following execution of one main processing instruction. RETI PR = 00: Specify level 0 with PR1 = 0, PR0 = 0 (higher priority level) PR = 01: Specify level 1 with PR1 = 0, PR0 = 1 PR = 10: Specify level 2 with PR1 = 1, PR0 = 0 PR = 11: Specify level 3 with PR1 = 1, PR0 = 1 (lower priority level) IE = 0: Interrupt request acknowledgment is disabled IE = 1: Interrupt request acknowledgment is enabled. RETI
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 20 INTERRUPT FUNCTIONS 20.4.4 Interrupt request hold There are instructions where, even if an interrupt request is issued while the instructions are being executed, interrupt request acknowledgment is held pending until the end of execution of the next instruction. These instructions (interrupt request hold instructions) are listed below. MOV PSW, #byte MOV PSW, A MOV1 PSW. bit, CY SET1 PSW. bit CLR1 PSW. bit RETB RETI POP PSW BTCLR PSW. bit, $addr20 EI DI SKC SKNC SKZ SKNZ SKH SKNH Manipulation instructions for the IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, IF3L, MK0L, MK0H, MK1L, MK1H, MK2L, MK2H, MK3L, PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR03L, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H, and PR13L registers Figure 20-11 shows the timing at which interrupt requests are held pending. CPU processing ××IF Figure 20-11. Interrupt Request Hold Instruction N Instruction M Remarks 1. Instruction N: Interrupt request hold instruction 2. Instruction M: Instruction other than interrupt request hold instruction PSW and PC saved, jump to interrupt servicing Interrupt servicing program R01UH0317EJ0004 Rev. 0.04 1072 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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19.2 Configuration of DMA Controlle
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34.2 64-pin products 1276 R5F10CLDx
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34.4 100-pin products 1278 CHAPTER
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