RL78/D1A User's Manual: Hardware - Renesas

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R01UH0317EJ0004 Rev. 0.04 1305 Feb. 22, 2013 Necessary WAIT I/O register(SFR) name R/W Bit R/W Address READ(MIN.) READ(MAX.) WRITE(MIN.) WRITE(MAX.) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1 8 16 7 6 5 4 3 2 1 0 Retry-number 2 +1 where the retry-number is calculated according F04D0 C1MDB0113 (CAN1 message data byte 01 register 13) - - E - - - - - - - - to the following method: (Abort under radix point) For read C1MDB013 - E - - - - - - - - - Min. (1/fCAN) 3/ (1/fCLK) F04D1 C1MDB113 - E - - - - - - - - - Max. (1/fCAN) 4/ (1/fCLK) C1MDB2313 (CAN1 message data byte 23 register 13) - - E - - - - - - - - For 8 bit-write F04D2 Min. (1/fCAN) 4/ (1/fCLK) Max. (1/fCAN) 5/ (1/fCLK) C1MDB213 - E - - - - - - - - - For 16 bit-write F04D3 C1MDB313 - E - - - - - - - - - Min. (1/fCAN) 2/ (1/fCLK) C1MDB4513 (CAN1 message data byte 45 register 13) - - E - - - - - - - - Max. (1/fCAN) 3/ (1/fCLK) F04D4 C1MDB413 - E - - - - - - - - - F04D5 C1MDB513 - E - - - - - - - - - F04D6 C1MDB6713 (CAN1 message data byte 67 register 13) - - E - - - - - - - - C1MDB613 - E - - - - - - - - - F04D7 C1MDB713 - E - - - - - - - - - F04D8 C1MDLC13 (CAN1 message data length register 13) - E - - - - - - - - - F04D9 C1MCONF13 (CAN1 message Configuration register 13) - E - - - - - - - - - F04DA C1MIDL13 (CAN1 message ID register 13L) - - E - - - - - - - - F04DC C1MIDH13 (CAN1 message ID register 13H) - - E - - - - - - - - F04DE C1MCTRL13 (CAN1 message control register 13) - - E - - - - - - - - F04E0 C1MDB0114 (CAN1 message data byte 01 register 14) - - E - - - - - - - - C1MDB014 - E - - - - - - - - - F04E1 C1MDB114 - E - - - - - - - - - F04E2 C1MDB2314 (CAN1 message data byte 23 register 14) - - E - - - - - - - - C1MDB214 - E - - - - - - - - - F04E3 C1MDB314 - E - - - - - - - - - F04E4 C1MDB4514 (CAN1 message data byte 45 register 14) - - E - - - - - - - - C1MDB414 - E - - - - - - - - - F04E5 C1MDB514 - E - - - - - - - - - F04E6 C1MDB6714 (CAN1 message data byte 67 register 14) - - E - - - - - - - - C1MDB614 - E - - - - - - - - - F04E7 C1MDB714 - E - - - - - - - - - F04E8 C1MDLC14 (CAN1 message data length register 14) - E - - - - - - - - - F04E9 C1MCONF14 (CAN1 message Configuration register 14) - E - - - - - - - - - 1305 RL78/D1A APPENDIX A NUMBER OF WAIT CYCLES TO ACCESS I/O REGISTERS Specifications in this document are tentative and subject to change. Under development Preliminary document
R01UH0317EJ0004 Rev. 0.04 1306 Feb. 22, 2013 Necessary WAIT I/O register(SFR) name R/W Bit R/W Address READ(MIN.) READ(MAX.) WRITE(MIN.) WRITE(MAX.) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1 8 16 7 6 5 4 3 2 1 0 Retry-number 2 +1 where the retry-number is calculated according F04EA C1MIDL14 (CAN1 message ID register 14L) - - E - - - - - - - - to the following method: (Abort under radix point) For read F04EC C1MIDH14 (CAN1 message ID register 14H) - - E - - - - - - - - Min. (1/fCAN) 3/ (1/fCLK) Max. (1/fCAN) 4/ (1/fCLK) F04EE C1MCTRL14 (CAN1 message control register 14) - - E - - - - - - - - For 8 bit-write F04F0 C1MDB0115 (CAN1 message data byte 01 register 15) - - E - - - - - - - - Min. (1/fCAN) 4/ (1/fCLK) Max. (1/fCAN) 5/ (1/fCLK) C1MDB015 - E - - - - - - - - - For 16 bit-write Min. (1/fCAN) 2/ (1/fCLK) F04F1 C1MDB115 - E - - - - - - - - - Max. (1/fCAN) 3/ (1/fCLK) F04F2 C1MDB2315 (CAN1 message data byte 23 register 15) - - E - - - - - - - - C1MDB215 - E - - - - - - - - - F04F3 C1MDB315 - E - - - - - - - - - F04F4 C1MDB4515 (CAN1 message data byte 45 register 15) - - E - - - - - - - - C1MDB415 - E - - - - - - - - - F04F5 C1MDB515 - E - - - - - - - - - F04F6 C1MDB6715 (CAN1 message data byte 67 register 15) - - E - - - - - - - - C1MDB615 - E - - - - - - - - - F04F7 C1MDB715 - E - - - - - - - - - F04F8 C1MDLC15 (CAN1 message data length register 15) - E - - - - - - - - - F04F9 C1MCONF15 (CAN1 message Configuration register 15) - E - - - - - - - - - F04FA C1MIDL15 (CAN1 message ID register 15L) - - E - - - - - - - - F04FC C1MIDH15 (CAN1 message ID register 15H) - - E - - - - - - - - F04FE C1MCTRL15 (CAN1 message control register 15) - - E - - - - - - - - F05C0 C0GMCTRL (CAN0 global module control register) - - E - - - - - - - - F05C6 C0GMABT (CAN0 global block transmission control register) - - E - - - - - - - - F05C8 C0GMABTD (CAN0 global block transmission delay setting register) - E - - - - - - - - - F05CE C0GMCS (CAN0 global module clock select register) - E - - - - - - - - - F05D0 C0MASK1L (CAN0 module mask 1 register L) - - E - - - - - - - - F05D2 C0MASK1H (CAN0 module mask 1 register H) - - E - - - - - - - - F05D4 C0MASK2L (CAN0 module mask 2 register L) - - E - - - - - - - - F05D6 C0MASK2H (CAN0 module mask 2 register H) - - E - - - - - - - - F05D8 C0MASK3L (CAN0 module mask 3 register L) - - E - - - - - - - - F05DA C0MASK3H (CAN0 module mask 3 register H) - - E - - - - - - - - 1306 RL78/D1A APPENDIX A NUMBER OF WAIT CYCLES TO ACCESS I/O REGISTERS Specifications in this document are tentative and subject to change. Under development Preliminary document
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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6.8 Operation of Plural Channels of
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