RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 6 TIMER ARRAY UNIT
(13) Sampling clock select register (TNFSMP0 to TNFSMP2)
Figure 6-28. Format of sampling clock select register (TNFSMP0 to TNFSMP2)
Address: F0061H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
TNFSMP0 NFSMP013 NFSMP012 NFSMP011 NFSMP010 NFSMP003 NFSMP002 NFSMP001 NFSMP000
Address: F0065H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
TNFSMP1 NFSMP113 NFSMP112 NFSMP111 NFSMP110 NFSMP103 NFSMP102 NFSMP101 NFSMP100
Address: F0069H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
TNFSMP2 NFSMP213 NFSMP212 NFSMP211 NFSMP210 NFSMP203 NFSMP202 NFSMP201 NFSMP200
n = 0, 1
NFSMPmn3 NFSMPmn2 NFSMPmn1 NFSMPmn0 Clock select
0 0 0 0 fCLK
0 0 0 1 fCLK/2
0 0 1 0 fCLK/2 2
0 0 1 1 fCLK/2 3
0 1 0 0 fCLK/2 4
0 1 0 1 fCLK/2 5
0 1 1 0 fCLK/2 6
0 1 1 1 fCLK/2 7
1 0 0 0 fCLK/2 8
1 0 0 1 fCLK/2 9
1 0 1 0 fMAIN
1 0 1 1 fMAIN/2
1 1 0 0 fMAIN/2 2
1 1 0 1 fMAIN/2 3
1 1 1 0 fMAIN/2 4
1 1 1 1 fIL
Note: In fact, NF clock is gated by TAUxEN. If not use TAU, NE is also disabled.
R01UH0317EJ0004 Rev. 0.04 353
Feb. 22, 2013