RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 31 INSTRUCTION SET Instruction Mnemonic Group Operands Bytes Bit manipulate XOR1 SET1 CLR1 Table 31-5. Operation List (14/17) Clocks Operation Flag Note 1 Note 2 Z AC CY CY, A.bit 2 1 CY CY A.bit CY, PSW.bit 3 1 CY CY PSW.bit CY, saddr.bit 3 1 CY CY (saddr).bit CY, sfr.bit 3 1 CY CY sfr.bit CY, [HL].bit 2 1 4 CY CY (HL).bit CY, ES:[HL].bit 3 2 5 CY CY (ES, HL).bit A.bit 2 1 A.bit 1 PSW.bit 3 4 PSW.bit 1 !addr16.bit 4 2 (addr16).bit 1 ES:!addr16.bit 5 3 (ES, addr16).bit 1 saddr.bit 3 2 (saddr).bit 1 sfr.bit 3 2 sfr.bit 1 [HL].bit 2 2 (HL).bit 1 ES:[HL].bit 3 3 (ES, HL).bit 1 A.bit 2 1 A.bit 0 PSW.bit 3 4 PSW.bit 0 !addr16.bit 4 2 (addr16).bit 0 ES:!addr16.bit 5 3 (ES, addr16).bit 0 saddr.bit 3 2 (saddr.bit) 0 sfr.bit 3 2 sfr.bit 0 [HL].bit 2 2 (HL).bit 0 ES:[HL].bit 3 3 (ES, HL).bit 0 SET1 CY 2 1 CY 1 1 CLR1 CY 2 1 CY 0 0 NOT1 CY 2 1 CY CY Notes 1. When the internal RAM area, SFR area, or extended SFR area is accessed, or for an instruction with no data access. 2. When the program memory area is accessed. Remark This number of clocks is for when the program is in the internal ROM (flash memory) area. When fetching an instruction from the internal RAM area, the number of clocks is twice the number of clocks plus 3, maximum. R01UH0317EJ0004 Rev. 0.04 1207 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 31 INSTRUCTION SET Instruction Mnemonic Group Operands Bytes Call/ return CALL Table 31-5. Operation List (15/17) Clocks Operation Flag Note 1 Note 2 Z AC CY rp 2 3 (SP 2) (PC + 2)S, (SP 3) (PC + 2)H, (SP 4) (PC + 2)L, PC CS, rp, SP SP 4 $!addr20 3 3 (SP 2) (PC + 3)S, (SP 3) (PC + 3)H, (SP 4) (PC + 3)L, PC PC + 3 + jdisp16, SP SP 4 !addr16 3 3 (SP 2) (PC + 3)S, (SP 3) (PC + 3)H, (SP 4) (PC + 3)L, PC 0000, addr16, SP SP 4 !!addr20 4 3 (SP 2) (PC + 4)S, (SP 3) (PC + 4)H, (SP 4) (PC + 4)L, PC addr20, SP SP 4 CALLT [addr5] 2 5 (SP 2) (PC + 2)S, (SP 3) (PC + 2)H, (SP 4) (PC + 2)L , PCS 0000, PCH (0000, addr5 + 1), PCL (0000, addr5), SP SP 4 BRK 2 5 (SP 1) PSW, (SP 2) (PC + 2)S, (SP 3) (PC + 2)H, (SP 4) (PC + 2)L, PCS 0000, PCH (0007FH), PCL (0007EH), SP SP 4, IE 0 RET 1 6 PCL (SP), PCH (SP + 1), PCS (SP + 2), SP SP + 4 RETI 2 6 PCL (SP), PCH (SP + 1), PCS (SP + 2), PSW (SP + 3), SP SP + 4 RETB 2 6 PCL (SP), PCH (SP + 1), PCS (SP + 2), PSW (SP + 3), SP SP + 4 R R R R R R Notes 1. When the internal RAM area, SFR area, or extended SFR area is accessed, or for an instruction with no data access. 2. When the program memory area is accessed. Remark This number of clocks is for when the program is in the internal ROM (flash memory) area. When fetching an instruction from the internal RAM area, the number of clocks is twice the number of clocks plus 3, maximum. R01UH0317EJ0004 Rev. 0.04 1208 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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