RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF) Figure 13-41. Timing of Occurrence of Data Consistency Error When BF Is Transmitted When UFnBRF = 1 (When Reception Is in Progress After Transmission of Stop Bit Has Stopped (Previous Input Data = 1)) LTxDn output LRxDn input Data sampling UFnBRF flag UFnTSF flag Error judgment (internal signal) UFnDCE flag INTLSn flag “1“ Edge detection BF length BF length Next transmission is not performed. R01UH0317EJ0004 Rev. 0.04 741 Feb. 22, 2013 Stop bit Stop bit Reception operation is stopped Figure 13-42. Timing of Occurrence of Data Consistency Error When BF Is Transmitted When UFnBRF = 1 (When Reception Is in Progress After Transmission of Stop Bit Has Started (Previous Input Data = 0)) LTxDn output LRxDn input Data sampling UFnBRF flag UFnTSF flag Error judgment (internal signal) UFnDCE flag INTLSn flag “1“ Edge detection BF length BF length During reception operation Stop bit Stop bit Next transmission is not performed. Edge detection (2) BF reception enable mode during communication (UFnMD1, UFnMD0 = 10B) If BF reception enable mode during communication (UFnMD1, UFnMD0 = 10B) is set, a mode that recognizes a new BF is entered during data communication in addition to when waiting for successful BF reception (UFnBRF = 1). When not waiting for successful BF reception (UFnBRF = 0) and when a low level has been detected at the data stop bit position (10th bit), judging a framing error or an overrun error is being waited for until input data becomes high level, because a new BF may be undergoing reception. If the successive-low-level period is less than 11 bits, it is judged as error detection (see Figure 13-43). If not an overrun error, the first eight bits of receive data are stored into the UFnRX register. At this time, a successful BF reception flag (UFnBSF) is not set. When
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF) waiting for successful BF reception (UFnBRF = 1), detecting framing or overrun errors and storing receive data into the UFnRX register are not performed. On the other hand, if the successive-low-level period is at least 11 bits, receiving of the new BF is judged successful and a successful BF reception flag (UFnBSF) is set (see Figure 13-44). Detection of framing or overrun errors is not performed. At this time, receive data is not stored into the UFnRX register. If a reception operation is stopped when starting to transmit the stop bit of data or a BF while UFnBRF is “0”, the data consistency error interrupt and flag are changed when the bit following the stop bit is started (see 13.5.8 (2)). If a reception operation is being performed when starting to transmit the stop bit, it is performed when input data “1” is detected at a position following the stop bit (see 13.5.8 (1) and Figure 13-45). On the other hand, if a reception operation is stopped when input data “1” is detected after stop bit transmission by setting UFnBRF to “1”, it is performed when the next bit is started (see Figure 13-46). During a reception operation, it is performed at a bit for which “1” is detected (see Figure 13-47). Caution To set to BF reception enable mode during communication (UFnMD1, UFnMD0 = 10B), be sure to set the UFnDCS bit of the UFnOPT1 register also to “1”. Figure 13-43. Framing Error/Overrun Error Judgment Timing upon BF Reception Failure (When UFnBRF = 0) LRxDn input Data sampling UFnFE flag/ UFnOVE flag UFnBSF flag INTLSn Remark n = 0, 1 “0“ Start bit D0 D5 D6 D7 When low-level period is less than 11 bits R01UH0317EJ0004 Rev. 0.04 742 Feb. 22, 2013 Stop bit
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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RL78/D1A User’s Manual: Hardware
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