RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 19 DMA CONTROLLER Figure 19-8. Example of Setting for CSI Consecutive Transmission Start DEN0 = 1 DSA0 = 10H/12H DRA0 = FB00H DBC0 = 0100H DMC0 = 4CH/4DH Setting for CSI transfer DST0 = 1 STG0 = 1 User program processing Occurrence of INTDMA0 DMA is started. INTCSI00/01 ccurs. DST0 = 0 Note DEN0 = 0 RETI End DMA0 transfer CSI transmission Hardware operation Note. The DST0 flag is automatically cleared to 0 when a DMA transfer is completed. Writing the DEN0 flag is enabled only when DST0 = 0. To terminate a DMA transfer without waiting for occurrence of the interrupt of DMA0 (INTDMA0), set the DST0 bit to 0 and then the DEN0 bit to 0 (for details, refer to 19.5.5 Forced termination by software). The fist trigger for consecutive transmission is not started by the interrupt of CSI. In this example, it start by a software trigger. CSI transmission of the second time and onward is automatically executed. A DMA interrupt (INTDMA0) occurs when the last transmit data has been written to the data register. R01UH0317EJ0004 Rev. 0.04 1039 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 19 DMA CONTROLLER 19.5.2 Consecutive capturing of A/D conversion results A flowchart of an example of setting for consecutively capturing A/D conversion results is shown below. Consecutive capturing of A/D conversion results. DMA channel 1 is used for DMA transfer. DMA start source: INTAD Interrupt of A/D is specified by IFC13 to IFC10 = 1110B. Transfers FFF1EH and FFF1FH (2 bytes) of the 10-bit A/D conversion result register (ADCR) to 512 bytes of FFCE0H to FFEDFH of RAM. Remark IFC13 to IFC10: Bits 3 to 0 of DMA mode control registers 1 (DMC1) R01UH0317EJ0004 Rev. 0.04 1040 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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12.5.3 Master transmission/receptio
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19.2 Configuration of DMA Controlle
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