RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 20 INTERRUPT FUNCTIONS CPU processing ××IF Figure 20-8. Interrupt Request Acknowledgment Timing (Minimum Time) Remark 1 clock: 1/fCLK (fCLK: CPU clock) CPU processing IF Instruction Instruction 6 clocks PSW and PC saved, jump to interrupt servicing 9 clocks Figure 20-9. Interrupt Request Acknowledgment Timing (Maximum Time) Instruction Remark 1 clock: 1/fCLK (fCLK: CPU clock) 8 clocks Instruction immediately before interrupt 16 clocks 6 clocks PSW and PC saved, jump to interrupt servicing Interrupt servicing program Interrupt servicing program R01UH0317EJ0004 Rev. 0.04 1067 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 20 INTERRUPT FUNCTIONS 20.4.2 Software interrupt request acknowledgment A software interrupt request is acknowledged by BRK instruction execution. Software interrupts cannot be disabled. If a software interrupt request is acknowledged, the contents are saved into the stacks in the order of the program status word (PSW), then program counter (PC), the IE flag is reset (0), and the contents of the vector table (0007EH, 0007FH) are loaded into the PC and branched. Restoring from a software interrupt is possible by using the RETB instruction. Caution Can not use the RETI instruction for restoring from the software interrupt. 20.4.3 Multiple interrupt servicing Multiple interrupt servicing occurs when another interrupt request is acknowledged during execution of an interrupt. Multiple interrupt servicing does not occur unless the interrupt request acknowledgment enabled state is selected (IE = 1). When an interrupt request is acknowledged, interrupt request acknowledgment becomes disabled (IE = 0). Therefore, to enable multiple interrupt servicing, it is necessary to set (1) the IE flag with the EI instruction during interrupt servicing to enable interrupt acknowledgment. Moreover, even if interrupts are enabled, multiple interrupt servicing may not be enabled, this being subject to interrupt priority control. Two types of priority control are available: default priority control and programmable priority control. Programmable priority control is used for multiple interrupt servicing. In the interrupt enabled state, if an interrupt request with a priority equal to or higher than that of the interrupt currently being serviced is generated, it is acknowledged for multiple interrupt servicing. If an interrupt with a priority lower than that of the interrupt currently being serviced is generated during interrupt servicing, it is not acknowledged for multiple interrupt servicing. Interrupt requests that are not enabled because interrupts are in the interrupt disabled state or because they have a lower priority are held pending. When servicing of the current interrupt ends, the pending interrupt request is acknowledged following execution of at least one main processing instruction execution. Table 20-5 shows relationship between interrupt requests enabled for multiple interrupt servicing and Figure 20-10 shows multiple interrupt servicing examples. R01UH0317EJ0004 Rev. 0.04 1068 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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34.2 64-pin products 1276 R5F10CLDx
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