RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF) Figure 13-64. Multi-Byte Transmission/Reception Processing Flow Example (2/2) TX Response transmitted? (Data length ≤ 9) UFnACE = 0? Yes Write transmit data (checksum) (UFnBUF1 to UFnBUF8 registers) UFnTW = 1, UFnCON = 0, UFnECS = ×, UFnNO = 0, UFnRRQ = 0, UFnTRQ = 1, UFnBUL3 to UFnBUL0 = ×H (UFnBUCTL register) END Yes Write transmit data (UFnBUF0 to UFnBUF7 registers) No No UFnACE = 0? Yes Write transmit data (checksum) (UFnBUF1 to UFnBUF8 registers) UFnTW = 0, UFnCON = 0, UFnECS = ×, UFnNO = 0, UFnRRQ = 0, UFnTRQ = 1, UFnBUL3 to UFnBUL0 = ×H (UFnBUCTL register) UFnTW = 0/1 Note , UFnCON = 1, UFnECS = ×, UFnNO = 0, UFnRRQ = 0, UFnTRQ = 1, UFnBUL3 to UFnBUL0 = ×H (UFnBUCTL register) R01UH0317EJ0004 Rev. 0.04 765 Feb. 22, 2013 C End upon next response? Yes Write transmit data (UFnBUF0 to UFnBUF7 registers) Note UFnTW is set to “1” during only the first data transmission after PID reception. END No No Write transmit data (UFnBUF0 to UFnBUF8 registers) Cautions 1. When the buffer length bits (UFnBUL3 to UFnBUL0) have been set to “0” or “10 to 15”, reception or transmission of nine bytes is performed. When the buffer length is set to “1 to 8”, buffers of the number of bytes set are used in ascending order of the buffer numbers. Example: When UFnBUL3 to UFnBUL0 are set to “1”, data is always stored only into the UFnBUF0 register. 2. Do not set the UFnRRQ bit when UFnBUC is “1”, because, when the UFnRRQ bit is set, storing (overwriting) into a buffer is performed even if reading receive data has not ended. 3. Setting the UFnTW bit is prohibited, except when operation is switched to response transmission after header reception. Remark : don’t care, n = 0, 1 END
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF) LTxDn pin LRxDn pin INTLSn INTLRn UFnHDC flag UFnBUC flag UFnRRQ bit UFnCON bit UFnTRQ bit UFnBUL3 to UFnBUL0 bits (write) UFnBUL3 to UFnBUL0 bits (read) “H” “L” “L” Figure 13-65. Multi-Byte Reception Implementation Example Response preparation Response preparation Response preparation check check check BF SF PID data data data data data CSF Sets UFnCLHDC bit to 1 Clear 0 1 Set Sets UFnRRQ bit to 1 Sets UFnCON bit to 1 R01UH0317EJ0004 Rev. 0.04 766 Feb. 22, 2013 Clear Sets UFnCLBUC bit to 1 Clear Sets UFnCLBUC bit to 1 Clear 2 2 2 2 0 1 2 0 1 2 Set Set Sets UFnRRQ bit to 1 Sets UFnRRQ bit to 1 Clears UFnCON bit to 0 Caution When UFnBUL3 to UFnBUL0 are “2”, data is always stored into UFnBUF0 and UFnBUF1. If read processing of the receive data is not performed in time, make adjustments such as setting UFnBUL3 to UFnBUL0 to “1”.
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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