RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF) 13.5.7 Parity types and operations Caution When using the LIN communication, fix the UFnPS1 and UFnPS0 bits of the UFnCTL0 register to 00 (n = 0, 1). The parity bit is used to detect bit errors in the communication data. Normally the same parity bit is used on the transmission side and the reception side. In the case of even parity and odd parity, it is possible to detect 1-bit (odd-count) errors. In the case of 0 parity and no parity, errors cannot be detected. (1) Even parity (a) During transmission The number of bits whose value is “1” among the transmit data, including the parity bit, is controlled so as to be an even number. The parity bit values are as follows. Odd number of bits whose value is “1” among transmit data: 1 Even number of bits whose value is “1” among transmit data: 0 (b) During reception The number of bits whose value is “1” among the reception data, including the parity bit, is counted, and if it is an odd number, a parity error is output. (2) Odd parity (a) During transmission Opposite to even parity, the number of bits whose value is “1” among the transmit data, including the parity bit, is controlled so that it is an odd number. The parity bit values are as follows. Odd number of bits whose value is “1” among transmit data: 0 Even number of bits whose value is “1” among transmit data: 1 (b) During reception The number of bits whose value is “1” among the receive data, including the parity bit, is counted, and if it is an even number, a parity error is output. (3) 0 parity During transmission, the parity bit is always made 0, regardless of the transmit data. During reception, parity bit check is not performed. Therefore, no parity error occurs, regardless of whether the parity bit is 0 or 1. (4) No parity No parity bit is added to the transmit data. Reception is performed assuming that there is no parity bit. No parity error occurs since there is no parity bit. R01UH0317EJ0004 Rev. 0.04 735 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF) LRxDn input Data sampling UFnPE flag INTLSn Figure 13-36. Parity Error Occurrence Timing Start bit D0 D1 D4 D5 D6 D7 13.5.8 Data consistency check When the data consistency check selection bit (UFnDCS) is set to “1”, transmit data and receive data are compared during transmission operation, even if the reception enable bit is disabled (UFnRXE = 0). When reception is enabled (UFnRXE = 1), it is also checked that reception processing is not ended early during transmission processing. When either a mismatch between transmission and reception signals or an early end of reception processing is detected during transmission processing, operation is judged as being abnormal, a status interrupt request signal (INTLSn) is output, and a data consistency error flag (UFnDCE) is set. Even if the next transmit data has already been written to the transmit data register (UFnTX), the next transmission is not performed. (The written data within UFnTX is ignored.) When the BF transmission trigger bit (UFnBTT) has been set, a BF is not transmitted. To restart transmission, transmit data must be written to the transmit data register (UFnTX) or the BF transmission trigger bit (UFnBTT) set after the end of transmission has been confirmed (UFnTSF = 0) and the data consistency error flag (UFnDCE) or the LINnEN bit of the PER0 register has been cleared. When a buffer is used, communication is stopped even if data not transferred remains in the buffer. When UFnRXE is “0”, storing receive data and thereby generating a reception complete interrupt request signal (INTLRn) as well as setting UFnBSF, UFnFE, and UFnOVE and thereby generating a status interrupt request signal (INTLSn) are not performed since the reception operation itself is not performed. Consequently, receive data is not required to be read. Caution A store operation of receive data is not affected by whether a data consistency error exists. Storing is performed even if a consistency error occurs. Remark n = 0, 1 R01UH0317EJ0004 Rev. 0.04 736 Feb. 22, 2013 Parity bit Stop bit
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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RL78/D1A User’s Manual: Hardware
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